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Static RAM. CY7C1020D Datasheet

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Static RAM. CY7C1020D Datasheet






CY7C1020D RAM. Datasheet pdf. Equivalent




CY7C1020D RAM. Datasheet pdf. Equivalent





Part

CY7C1020D

Description

512-Kbit (32 K x 16) Static RAM



Feature


CY7C1020D 512-Kbit (32 K × 16) Static R AM 512-Kbit (32 K × 16) Static RAM Fe atures ■ Pin- and function-compatible with CY7C1020B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA @ 10 ns ■ Low complementary met al oxide semiconductor (CMOS) standby p ower ❐ ISB2 = 3 mA ■ 2.0 V data ret ention ■ Automatic power-down when de selected ■ CMOS for optimum speed/powe.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1020D Datasheet


Cypress Semiconductor CY7C1020D

CY7C1020D; r ■ Independent control of upper and l ower bits ■ Available in Pb-free 44-p in 400-Mil wide Molded SOJ and 44-pin t hin small outline package (TSOP) II pac kages Functional Description The CY7C10 20D [1] is a high-performance CMOS stat ic RAM organized as 32,768 words by 16 bits. This device has an automatic powe r-down feature that significantly reduc es power consumption w.


Cypress Semiconductor CY7C1020D

hen deselected.The input and output pins (IO0 through IO15) are placed in a hig h-impedance state when: Logic Block Di agram DATA IN DRIVERS ■ Deselected (CE HIGH) ■ Outputs are disabled (OE HIGH) ■ BHE and BLE are disabled (BH .


Cypress Semiconductor CY7C1020D

.

Part

CY7C1020D

Description

512-Kbit (32 K x 16) Static RAM



Feature


CY7C1020D 512-Kbit (32 K × 16) Static R AM 512-Kbit (32 K × 16) Static RAM Fe atures ■ Pin- and function-compatible with CY7C1020B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA @ 10 ns ■ Low complementary met al oxide semiconductor (CMOS) standby p ower ❐ ISB2 = 3 mA ■ 2.0 V data ret ention ■ Automatic power-down when de selected ■ CMOS for optimum speed/powe.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1020D Datasheet




 CY7C1020D
CY7C1020D
512-Kbit (32 K × 16) Static RAM
512-Kbit (32 K × 16) Static RAM
Features
Pin- and function-compatible with CY7C1020B
High speed
tAA = 10 ns
Low active power
ICC = 80 mA @ 10 ns
Low complementary metal oxide semiconductor (CMOS)
standby power
ISB2 = 3 mA
2.0 V data retention
Automatic power-down when deselected
CMOS for optimum speed/power
Independent control of upper and lower bits
Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin thin small outline package (TSOP) II packages
Functional Description
The CY7C1020D [1] is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.The input and output pins
(IO0 through IO15) are placed in a high-impedance state when:
Logic Block Diagram
DATA IN DRIVERS
Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
BHE and BLE are disabled (BHE, BLE HIGH)
When the write operation is active (CE LOW, and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7), is written into the location
specified on the address pins (A0 through A14). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A14).
Reading from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 11 for a
complete description of read and write modes.
The CY7C1020D device is suitable for interfacing with
processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
For a complete list of related documentation, click here.
A7
A6
A5
A4
A3
32K x 16
RAM Array
A2
A1
A0
IO0–IO7
IO8–IO15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05463 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 28, 2014




 CY7C1020D
CY7C1020D
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Document Number: 38-05463 Rev. *J
Page 2 of 17




 CY7C1020D
CY7C1020D
Pin Configurations
Figure 1. 44-pin SOJ/TSOP II pinout (Top View) [2]
NC
A3
A2
A1
A0
CE
IO0
IO1
IO2
IO3
VCC
VSS
IO4
IO5
IO6
IO7
WE
AA144
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 IO15
37 IO14
36 IO13
35 IO12
34 VSS
33 VCC
32
31
IIOO1110
30 IO9
29 IO8
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
-10 (Industrial)
10
80
3
Unit
ns
mA
mA
Note
2. NC pins are not connected on the die.
Document Number: 38-05463 Rev. *J
Page 3 of 17



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