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Network Processor. CY7C53150 Datasheet

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Network Processor. CY7C53150 Datasheet






CY7C53150 Processor. Datasheet pdf. Equivalent




CY7C53150 Processor. Datasheet pdf. Equivalent





Part

CY7C53150

Description

Neuron Chip Network Processor



Feature


CY7C53150, CY7C53120 Neuron Chip Network Processor Features ■ Three 8-bit pi pelined processors for concurrent proce ssing of application code and network t raffic ■ 11-pin I/O port programmable in 34 modes for fast application progr am development ■ Two 16-bit timer/cou nters for measuring and generating I/O device waveforms ■ 5-pin communicatio n port that supports direc.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C53150 Datasheet


Cypress Semiconductor CY7C53150

CY7C53150; t connect and network transceiver interf aces ■ Programmable pull-ups on I/O4 I/O7 and 20 mA sink current on I/O0 I/O3 ■ Unique 48-bit ID number in ev ery device to facilitate network instal lation and management ■ Low operating current; sleep mode operation for redu ced current consumption[1] ■ 0.35  m flash process technology ■ 5.0 V op eration ■ On-chip LVD circuit to .


Cypress Semiconductor CY7C53150

prevent nonvolatile memory corruption du ring voltage drops ■ 2,048 bytes of S RAM for buffering network data, system, and application data storage ■ 512 b ytes (CY7C53150), 2048 bytes (CY7C53120 E2), 4096 bytes (CY7C53120E4) of Flash .


Cypress Semiconductor CY7C53150

.

Part

CY7C53150

Description

Neuron Chip Network Processor



Feature


CY7C53150, CY7C53120 Neuron Chip Network Processor Features ■ Three 8-bit pi pelined processors for concurrent proce ssing of application code and network t raffic ■ 11-pin I/O port programmable in 34 modes for fast application progr am development ■ Two 16-bit timer/cou nters for measuring and generating I/O device waveforms ■ 5-pin communicatio n port that supports direc.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C53150 Datasheet




 CY7C53150
CY7C53150, CY7C53120
Neuron Chip Network Processor
Features
Three 8-bit pipelined processors for concurrent processing of
application code and network traffic
11-pin I/O port programmable in 34 modes for fast application
program development
Two 16-bit timer/counters for measuring and generating I/O
device waveforms
5-pin communication port that supports direct connect and
network transceiver interfaces
Programmable pull-ups on I/O4–I/O7 and 20 mA sink current
on I/O0–I/O3
Unique 48-bit ID number in every device to facilitate network
installation and management
Low operating current;
current consumption[1]
sleep
mode
operation
for
reduced
0.35 m flash process technology
5.0 V operation
Logic Block Diagram
On-chip LVD circuit to prevent nonvolatile memory corruption
during voltage drops
2,048 bytes of SRAM for buffering network data, system, and
application data storage
512 bytes (CY7C53150), 2048 bytes (CY7C53120E2), 4096
bytes (CY7C53120E4) of Flash memory with on-chip charge
pump for flexible storage of configuration data and application
code
Addresses up to 58 KB of external memory (CY7C53150)
10 KB (CY7C53120E2), 12 KB (CY7C53120E4) of ROM
containing LonTalk network protocol firmware
Maximum input clock operation of 20 MHz (CY7C53150),
10 MHz (CY7C53120E2), 40 MHz (CY7C53120E4) over a
–40°C to 85°C[2] temperature range
64-pin TQFP package (CY7C53150)
32-pin SOIC or 44-pin TQFP package (CY7C53120)
Media Access
Control Processor
Network
Processor
Application
Processor
2 KB RAM
Flash
ROM
(CY7C53120)
Internal
Data Bus
(0:7)
Internal
Address Bus
(0:15)
Communications
Port
I/O Block
2 Timer/
Counters
CP4
CP0
I/O10
I/O0
Oscillator,
Clock, and
Control
CLK1
CLK2
SERVICE
RESET
External
Address/Data Bus
(CY7C53150)
Notes
1. Rare combinations of wake-up events occurring during the go to sleep sequence could produce unexpected sleep behavior.
2. Maximum Junction Temperature is 105 °C. TJunction = TAmbient + V•I•JA. 32-pin SOIC JA = 51 °C/W. 44-pin TQFP JA = 43 °C/W. 64-pin TQFP JA = 44 °C/W.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-10001 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 16, 2017




 CY7C53150
CY7C53150, CY7C53120
Contents
Functional Description ..................................................... 3
Pin Configurations ........................................................... 4
Pin Descriptions ............................................................... 6
Memory Usage .................................................................. 7
Flash Memory Retention and Endurance ....................... 7
40 MHz 3120 Operation .................................................... 7
Low Voltage Inhibit Operation ......................................... 7
Communications Port ...................................................... 7
Programmable Hysteresis Values ............................... 8
Programmable Glitch Filter Values[7] ........................... 8
Receiver[8] (End-to-End) Absolute Asymmetry ........... 8
Differential Receiver (End-to-End)
Absolute Symmetry[9, 10] ..................................................... 8
Electrical Characteristics ................................................. 9
LVI Trip Point (VDD) ........................................................... 9
External Memory Interface Timing — CY7C53150 ....... 10
Differential Transceiver Electrical Characteristics ...... 10
Ordering Information[23] ............................................... 14
Ordering Code Definitions ......................................... 14
Package Diagrams .......................................................... 15
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 38-10001 Rev. *L
Page 2 of 19




 CY7C53150
CY7C53150, CY7C53120
Functional Description
The CY7C531x0 Neuron chip implements a node for LonWorks
distributed intelligent control networks. It incorporates, on a
single chip, the necessary communication and control functions,
both in hardware and firmware, that facilitate the design of a
LonWorks node.
The CY7C531x0 contains a very flexible 5-pin communication
port that can be configured to interface with a wide variety of
media transceivers at a wide range of data rates. The most
common transceiver types are twisted-pair, powerline, RF, IR,
fiber-optics, and coaxial.
The CY7C531x0 is manufactured using state of the art 0.35 m
Flash technology, providing to designers the most cost-effective
Neuron chip solution.
Services at every layer of the OSI networking reference model
are implemented in the LonTalk firmware based protocol stored
in 10-KB ROM (CY7C53120E2), 12-KB ROM (CY7C53120E4),
or off-chip memory (CY7C53150). The firmware also contains 34
preprogrammed I/O drivers, greatly simplifying application
programming. The application program is stored in the Flash
memory (CY7C53120) and/or off-chip memory (CY7C53150),
and may be updated by downloading over the network.
The CY7C53150 incorporates an external memory interface that
can address up to 64 KB with 6 KB of the address space mapped
internally. LonWorks nodes that require large application
programs can take advantage of this external memory capability.
The CY7C53150 Neuron chip is an exact replacement for the
Motorola MC143150Bx and Toshiba TMPN3150B1 devices. The
CY7C53120E2 Neuron chip is an exact replacement for the
Motorola MC143120E2 device since it contains the same
firmware in ROM.
Document Number: 38-10001 Rev. *L
Page 3 of 19



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