DatasheetsPDF.com

256-Kbit nvSRAM. CY14E256LA Datasheet

DatasheetsPDF.com

256-Kbit nvSRAM. CY14E256LA Datasheet






CY14E256LA nvSRAM. Datasheet pdf. Equivalent




CY14E256LA nvSRAM. Datasheet pdf. Equivalent





Part

CY14E256LA

Description

256-Kbit nvSRAM



Feature


CY14E256LA 256-Kbit (32 K × 8) nvSRAM 256-Kbit (32 K × 8) nvSRAM Features 25 ns and 45 ns access times ■ Inte rnally organized as 32 K × 8 (CY14E256 LA) ■ Hands-off automatic STORE on po wer-down with only a small capacitor STORE to QuantumTrap nonvolatile elem ents initiated by software, device pin, or autostore on power-down ■ RECALL to SRAM initiated by software o.
Manufacture

Cypress Semiconductor

Datasheet
Download CY14E256LA Datasheet


Cypress Semiconductor CY14E256LA

CY14E256LA; r power-up ■ Infinite read, write, and RECALL cycles ■ 1 million STORE cycl es to QuantumTrap ■ 20-year data rete ntion ■ Single 5 V + 10% operation Industrial temperature ■ 44-pin thi n small-outline package (TSOP) Type II and 32-pin small-outline integrated cir cuit (SOIC) package ■ Pb-free and res triction of hazardous substances (RoHS) compliant Functional Descripti.


Cypress Semiconductor CY14E256LA

on The Cypress CY14E256LA is a fast stat ic RAM, with a nonvolatile element in e ach memory cell. The memory is organize d as 32 KB. The embedded nonvolatile el ements incorporate QuantumTrap technolo gy, producing the world’s most reli .


Cypress Semiconductor CY14E256LA

.

Part

CY14E256LA

Description

256-Kbit nvSRAM



Feature


CY14E256LA 256-Kbit (32 K × 8) nvSRAM 256-Kbit (32 K × 8) nvSRAM Features 25 ns and 45 ns access times ■ Inte rnally organized as 32 K × 8 (CY14E256 LA) ■ Hands-off automatic STORE on po wer-down with only a small capacitor STORE to QuantumTrap nonvolatile elem ents initiated by software, device pin, or autostore on power-down ■ RECALL to SRAM initiated by software o.
Manufacture

Cypress Semiconductor

Datasheet
Download CY14E256LA Datasheet




 CY14E256LA
CY14E256LA
256-Kbit (32 K × 8) nvSRAM
256-Kbit (32 K × 8) nvSRAM
Features
25 ns and 45 ns access times
Internally organized as 32 K × 8 (CY14E256LA)
Hands-off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or autostore on power-down
RECALL to SRAM initiated by software or power-up
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
20-year data retention
Single 5 V + 10% operation
Industrial temperature
44-pin thin small-outline package (TSOP) Type II and 32-pin
small-outline integrated circuit (SOIC) package
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14E256LA is a fast static RAM, with a
nonvolatile element in each memory cell. The memory is
organized as 32 KB. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
For a complete list of related documentation, click here.
Logic Block Diagram
A5
A6
A7
A8
A9
A 11
A 12
A 13
A 14
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
QuantumTrap
512 X 512
STORE
STATIC RAM
ARRAY
512 X 512
RECALL
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
-A13 A0
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-54952 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 14, 2014




 CY14E256LA
CY14E256LA
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ................................................................ 4
SRAM Write ................................................................. 4
AutoStore Operation .................................................... 4
Hardware STORE Operation ....................................... 4
Hardware RECALL (Power-up) ................................... 5
Software STORE ......................................................... 5
Software RECALL ....................................................... 5
Preventing AutoStore .................................................. 6
Data Protection ............................................................ 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Data Retention and Endurance ....................................... 8
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Loads .................................................................. 9
AC Test Conditions .......................................................... 9
AC Switching Characteristics ....................................... 10
SRAM Read Cycle .................................................... 10
SRAM Write Cycle ..................................................... 10
Switching Waveforms .................................................... 10
AutoStore/Power-up RECALL ....................................... 12
Switching Waveforms .................................................... 12
Software Controlled STORE/RECALL Cycle ................ 13
Switching Waveforms .................................................... 13
Hardware STORE Cycle ................................................. 14
Switching Waveforms .................................................... 14
Truth Table For SRAM Operations ................................ 15
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC Solutions ......................................................... 19
Document Number: 001-54952 Rev. *K
Page 2 of 19




 CY14E256LA
CY14E256LA
Pinouts
Figure 1. 44-pin TSOP II / 32-pin SOIC pinout
NC
NC[5]
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
NC
NC
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8
9
44-pin TSOP II
37
36
10 (x 8)
35
11
12 Top View
13 (not to scale)
14
34
33
32
31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
HSB
NC
NNCC[[43]]
NC[2]
NC [1]
NC [1]
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
VCAP
A14
A13
A12
A11
A10
NC
NC
32-pin SOIC
(x 8)
Top View
(not to scale)
Pin Definitions
Pin Name I/O Type
Description
A0–A14
DQ0–DQ7
WE
Input Address inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Input/Output Bidirectional data I/O Lines. Used as input or output lines depending on operation.
Input
Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
CE Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tri-stated on deasserting OE HIGH.
VSS
VCC
HSB
Ground Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the device.
Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
is optional).
VCAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC No connect No connect. This pin is not connected to the die.
Notes
1. Address expansion for 1-Mbit. NC pin not connected to die.
2. Address expansion for 2-Mbit. NC pin not connected to die.
3. Address expansion for 4-Mbit. NC pin not connected to die.
4. Address expansion for 8-Mbit. NC pin not connected to die.
5. Address expansion for 16-Mbit. NC pin not connected to die.
Document Number: 001-54952 Rev. *K
Page 3 of 19



Recommended third-party CY14E256LA Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)