ATMLH412 EEPROM Datasheet

ATMLH412 Datasheet, PDF, Equivalent


Part Number

ATMLH412

Description

Two-wire Serial EEPROM

Manufacture

ATMEL

Total Page 12 Pages
Datasheet
Download ATMLH412 Datasheet


ATMLH412
Features
Low-voltage and Standard-voltage Operation
1.8 (V = 1.8V to 5.5V)
CC
Internally Organized as 32,768 x 8
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5.0V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
64-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Max)
High Reliability
Endurance: One Million Write Cycles
Data Retention: 40 Years
Lead-free/Halogen-free Devices Available
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC, 8-lead Ultra Thin Small
Array Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages
Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Description
The ATMLH412 provides 262,144 bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 32,768 words of 8 bits
each. The device’s cascadable feature allows up to eight devices to share a common
two-wire bus. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The devices
are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra
Thin SAP, 8-lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is
available in a 1.8V (1.8V to 5.5V) version.
Table 1. Pin Configurations
Pin Name
A0 – A2
SDA
SCL
Function
Address Inputs
Serial Data
Serial Clock Input
WP Write Protect
GND
Ground
8-lead PDIP
A0 1
A1 2
8 VCC
7 WP
A2 3
6 SCL
GND 4
5 SDA
A0
A1
A2
GND
8-lead SOIC
18
27
36
45
VCC
WP
SCL
SDA
8-ball dBGA2
VCC 8
WP 7
1 A0
2 A1
SCL 6 3 A2
SDA 5 4 GND
Bottom View
8-lead TSSOP
A0 1
A1 2
8 VCC
7 WP
A2 3
6 SCL
GND 4
5 SDA
8-lead Ultra-Thin SAP
VCC 8
1 A0
WP 7 2 A1
SCL 6 3 A2
SDA 5 4 GND
Bottom View
Two-wire
Serial EEPROM
256K (32,768 x 8)
ATMLH412
8568A–SEEPR–11/08

ATMLH412
Absolute Maximum Ratings*
Operating Temperature...........................• 55°C to +125°C
Storage Temperature ............................• 65°C to + 150°C
Voltage on Any Pin
with Respect to Ground................................ • 1.0 V +7.0V
Maximum Operating Voltage.....................................6.25V
DC Output Current ..................................................5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions beyond those indicated in
the operational sections of this specification are
not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
Figure 1.
VCC
GND
WP
SCL
SDA
A2
A1
A0
Block Diagram
START
STOP
LOGIC
LOAD
DEVICE
ADDRESS
COMPARATOR
SERIAL
CONTROL
EN
H.V. PUMP/TIMING
LOGIC
COMP
LOAD INC
DATA RECOVERY
R/W DATA WORD
ADDR/COUNTER
EEPROM
DIN
DOUT
Y DEC
SERIAL MUX
DOUT/ACK
LOGIC
8568A–SEEPR–11/08


Features Features • Low-voltage and Standard-vo ltage Operation ⎯ 1.8 (V = 1.8V to 5. 5V) CC • Internally Organized as 32,7 68 x 8 • Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression • Bidirectional Dat a Transfer Protocol • 1 MHz (5.0V, 2. 7V, 2.5V), and 400 kHz (1.8V) Compatibi lity • Write Protect Pin for Hardware and Software Data Protection • 64-by te Page Write Mode (Partial Page Writes Allowed) • Self-timed Write Cycle (5 ms Max) • High Reliability ⎯ Endur ance: One Million Write Cycles ⎯ Data Retention: 40 Years • Lead-free/Halo gen-free Devices Available • 8-lead J EDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC , 8-lead Ultra Thin Small Array Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages • Die Sales: Wafer Form, Waf fle Pack and Bumped Wafers Description The ATMLH412 provides 262,144 bits of serial electrically erasable and progra mmable read-only memory (EEPROM) organi zed as 32,768 words of 8 bits each. The device’s cascadable f.
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