WESTCODE An IXYS Company
Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#
2.1 Instantaneous on-state voltage
Measured using a 500µs square pulse, see also the curves of figure 2 for other values of ITM.
2.2 Latching and holding current
These are considered to be approximately equal and only the latching current is measured, type test only
as outlined below. The test circuit and wave diagrams are given in diagram 4. The anode current is
monitored on an oscilloscope while VD is increased, until the current is seen to flow during the un-gated
period between the end of IG and the application of reverse gate voltage. Test frequency is 100Hz with IGM
& IG as for td of characteristic data.
Diagram 4, Latching test circuit and waveforms.
2.3 Critical dv/dt
The gate conditions are the same as for 1.1, this characteristic is for off-state only and does not relate to
dv/dt at turn-off. The measurement, type test only, is conducted using the exponential ramp method as
shown in diagram 5. It should be noted that GTO thyristors have a poor static dv/dt capability if the gate is
open circuit or RGK is high impedance. Typical values: - dv/dt<30V/µs for RGK>10Ω.
Diagram 5, Definition of dV/dt.
2.4 Off-state leakage.
For IDRM & IRRM see notes 1.1 & 1.2 for gate leakage IGK, the off-state gate circuit is required to sink this
leakage and still maintain minimum of –2 Volts. See diagram 6.
Data Sheet. Type H0500KC25# Issue 2
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