translating buffer. 74AXP1T34 Datasheet

74AXP1T34 buffer. Datasheet pdf. Equivalent

Part 74AXP1T34
Description Dual supply translating buffer
Feature 74AXP1T34 Dual supply translating buffer Rev. 1 — 22 December 2015 Product data sheet 1. General d.
Manufacture nexperia
Datasheet
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74AXP1T34 Dual supply translating buffer Rev. 1 — 22 Decembe 74AXP1T34 Datasheet
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74AXP1T34
74AXP1T34
Dual supply translating buffer
Rev. 1 — 22 December 2015
Product data sheet
1. General description
The 74AXP1T34 is a dual supply translating buffer. It features one input (A), an output (Y)
and dual supply pins (VCCI and VCCO). The inputs are referenced to VCCI and the output is
referenced to VCCO. All inputs can be connected directly to VCCI or GND. VCCI can be
supplied at any voltage between 0.7 V and 2.75 V and VCCO can be supplied at any
voltage between 1.2 V and 5.5 V. This feature allows voltage level translation.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times.
This device ensures very low static and dynamic power consumption across the entire
supply range and is fully specified for partial power down applications using IOFF. The IOFF
circuitry disables the output, preventing the potentially damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range:
VCCI: 0.7 V to 2.75 V
VCCO: 1.2 V to 5.5 V
Low input capacitance; CI = 0.6 pF (typical)
Low output capacitance; CO = 1.8 pF (typical)
Low dynamic power consumption; CPD = 0.4 pF at VCCI = 1.2 V (typical)
Low dynamic power consumption; CPD = 7.1 pF at VCCO = 3.3 V (typical)
Low static power consumption; ICCI = 0.5 A (85 C maximum)
Low static power consumption; ICCO = 1.8 A (85 C maximum)
High noise immunity
Complies with JEDEC standard:
JESD8-12A.01 (1.1 V to 1.3 V; A input)
JESD8-11A.01 (1.4 V to 1.6 V)
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A.01 (2.3 V to 2.7 V)
JESD8-C (2.7 V to 3.6 V; Y output)
JESD12-6 (4.5 V to 5.5 V; Y output)
ESD protection:
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM JESD22-C101E exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD78D Class II
Inputs accept voltages up to 2.75 V



74AXP1T34
Nexperia
74AXP1T34
Dual supply translating buffer
Low noise overshoot and undershoot < 10% of VCCO
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from 40 C to +85 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74AXP1T34GW 40 C to +85 C TSSOP5
74AXP1T34GM 40 C to +85 C XSON6
74AXP1T34GN 40 C to +85 C XSON6
74AXP1T34GS 40 C to +85 C XSON6
74AXP1T34GX 40 C to +85 C X2SON5
Description
Version
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 1.45 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
SOT1202
X2SON5: plastic thermal enhanced extremely thin
small outline package; no leads; 5 terminals;
body 0.8 0.8 0.35 mm
SOT1226
4. Marking
Table 2. Marking
Type number
74AXP1T34GW
74AXP1T34GM
74AXP1T34GN
74AXP1T34GS
74AXP1T34GX
Marking code[1]
rQ
rQ
rQ
rQ
rQ
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
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Fig 1. Logic symbol
DDF
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9&&,
Fig 2. Logic diagram
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9&&2
DDD
74AXP1T34
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2015
.
2 of 21
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