LATCHED DRIVER. M54992P Datasheet

M54992P DRIVER. Datasheet pdf. Equivalent

Part M54992P
Description Bi-CMOS 24-BIT SERIAL-INPUT LATCHED DRIVER
Feature MITSUBISHI M54992P/FP Bi-CMOS 24-BIT SERIAL-INPUT LATCHED DRIVER DESCRIPTION .
Manufacture Mitsubishi
Datasheet
Download M54992P Datasheet

MITSUBISHI M54992P/FP Bi-CMOS 24-BIT M54992P Datasheet
MITSUBISHI M54992P/FP Bi-CMOS 24-BIT S M54992P Datasheet
Recommendation Recommendation Datasheet M54992P Datasheet





M54992P
MITSUBISHI <CONTROL / DRIVER IC>
M54992P/FP
Bi-CMOS 24-BIT SERIAL-INPUT LATCHED DRIVER
DESCRIPTION
The M54992 is a semiconductor integrated circuit consisting of 24
stages of CMOS shift registers and latches with serial inputs and
serial or parallel outputs. It is based on Bi-CMOS process
technology, and has 24 bipolar drivers at the parallel outputs.
FEATURES
q Serial input and serial or parallel output
q Serial output enables cascade connection
q Built-in latch for each stage
q Enable input provides output control
q Low supply current (standby current ICC1mA)
q Serial I/O level is compatible with typical CMOS devices
q Driver features: High withstand voltage (BVCEO30V)
Capable of large drive currents (IO(max)=100mA)
q Wide operating temperrature range Ta=-10 – +75°C
APPLICATION
Dot drivers of thermal printer heads, serial/parallel conversion.
Drivers for relays and solenoids.
FUNCTION
The M54992 consists of 24 stages of D-type flip flops connected to
24 latches.
Data is input to serial input S-IN, and clock pulses are input to
clock input T. When the clock changes from low to high, the input
data enters the first shift register and data already in the shift
registers is shifted sequentially.
The serial output S-OUT is used to connect multiple M54992 to
expand the number of parallel outputs. S-OUT is connected to S-IN
of the next stage.
For parallel output. When the clock pulse changes from low to
high, latch input (LATCH) is high and output enable input (EN) is
low the serial input data at S-IN appears at output O1 and the other
data already present is shifted sequentially to outputs O2 through
O24.
The parallel outputs are inverted.
When the latch input is held low, the latch retains the stored data.
When the EN input is high, outputs O1 through O24 all turn off. As
the internal logic is unstable when the power is turned on, the EN
input should be kept high (setting outputs O1 through O24 off) until
input data is set and the internal logic is initialized.
L-GND is the GND of CMOS logic circuit and P-GND is the GND of
output driver circuits O1 through O24 which employ bipolar
transistors capable of large drive currents.
An output load prevention circuit is built in this IC to prevent
misoperation at power ON/OFF. Therefore, when VCC falls short of
the fixed level, all outputs (O1 – O24) are compulsorily set to the
OFF state.
PIN CONFIGURATION (TOP VIEW)
GND 1
O6 2
O5 3
Parallel outputs
O4 4
O3 5
O2 6
O1 7
Serial input S-IN 8
Clock
T9
Latch input LATCH 10
O24 11
Parallel outputs
O23 12
O22 13
O21 14
NC 15
Parallel outputs
O20 16
O19 17
GND 18
36 GND
35 O7
34 O8
Parallel outputs
33 NC
32 O9
31 O10
30 O11
Parallel outputs
29 O12
28 EN Enable input
27 VCC
26 O13
25 O14
24 O15
Parallel outputs
23 O16
22 NC
21 O17
20 O18
Parallel outputs
19 GND
Outline 36P4E
Enable input EN 1
O12 2
O11 3
Parallel outputs
O10 4
O9 5
O8 6
O7 7
8
GND 9
10
O6 11
O5 12
Parallel outputs
O4 13
O3 14
O2 15
Serial input
Clock
O1 16
S-IN 17
T 18
36 VCC
35 O13
34 O14
33 O15
32 O16
Parallel outputs
31 O17
30 O18
29
28 GND
27
26 O19
25 O20
24 O21
23 O22
Parallel outputs
22 O23
21 O24
20 SO
Serial input
19 LATCH Latch input
Outline 36P2R-A
NC: no connection



M54992P
MITSUBISHI <CONTROL / DRIVER IC>
M54992P/FP
Bi-CMOS 24-BIT SERIAL-INPUT LATCHED DRIVER
BLOCK DIAGRAM
O1 O2 O3 O4 O5 O6
Parallel outputs
O12 O13
––
O19 O20 O21 O22 O23 O24
Q
LD
Q
LD
Q
LD
QQ
LD LD
QQQQQ
LD LD LD LD LD
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
GND
TRUTH TABLE
S-IN
L
L
H
H
H
Input
Output
T LATCH EN O1–O24 S-OUT
IN L
L t-1 L
IN H L L L
IN L
L t-1 H
IN H L H H
IN H H L H
T: IN means to input following signal
12
23 24
L : low level
H : high level
t-1 : previous state
H output : OFF state
L output : ON state





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)