TRANSISTOR ARRAY. LS159 Datasheet

LS159 ARRAY. Datasheet pdf. Equivalent

Part LS159
Description HIGH RELIABILITY TRANSISTOR ARRAY
Feature LINEAR INTEGRATED CIRCUIT HIGH RELIABILITY TRANSISTOR ARRAY The LS159 is an array of 5 NPN transist.
Manufacture SGS
Datasheet
Download LS159 Datasheet

LINEAR INTEGRATED CIRCUIT HIGH RELIABILITY TRANSISTOR ARRAY LS159 Datasheet
Recommendation Recommendation Datasheet LS159 Datasheet




LS159
LINEAR INTEGRATED CIRCUIT
HIGH RELIABILITY TRANSISTOR ARRAY
The LS159 is an array of 5 NPN transistors on a common monolithic substrate in an SO-14 (14-lead
plastic micropackage). This package is easily mounted on thick and thin film hybrid circuits. Two
transistors are internally connected to form a differential amplifier. The transistors of the LS159 are well
suited to low noise general purposes and to a wide variety of applications in low power systems in the
DC through VHF range. They may be used as discrete components in conventional circuits; in addition
they provide the very significant inherent integrated circuit advantages of close electrical and thermal
matching. The device is also available with a ermetic goldchip (LS8159M) that is particularly suitable
for professional and telecom applications, wherever very high MTBF are required. This performance is
guaranteed by silicon nitride sealing of chip surface and Ti-Pt-Au metallization, protected with a double
passivated layer, providing resistance against contamination, electrolytic corrosion and electromigration.
ABSOLUTE MAXIMUM RATINGS
Each
Total
transistor package
V C60
V CEO
Vcss *
V E60
Ic
Ptot
Tstg ' TJ
Collector-base voltage (I E = 0)
Collector-emitter voltage (16= 0)
Collector--substrate voltage
Emitter-base voltage (lc= 0)
Collector current
Total power dissipation at Tamb= 25°C
Storage, and junction temperature
Soldering dip or wave at 5 s
11 s
20V
15 V
20V
5V
50mA
,250 mW 500 mW
-55 to 150°C
260 °C
235°C
*) The collector of each transistor of the LS159 is isolated from the substrate by an integrated diode.
The substrate (pin 13) must be connected to the most negative point in the external circuit to maintain isolation
between transistors and to provide for normal transistor action.
ORDERING NUMBERS: LS 159M - LS 8159M
MECHANICAL DATA
Dimensions in mm
271 6/82



LS159
SCHEMATIC DIAGRAM
2
54
8
11 14
3
5-3763
6 7 9 10 12 13
subst rate
THERMAL DATA
Rth j-amb Thermal resistance junction-ambient
max 250 °e!W
ELECTRICAL CHARACTERISTICS (Tamb = 25°e unless otherwise specified)
Parameter
Test conditions
Min.
Typ.
Max. Unit Fig.
ICBO
I CEO
II B1-I B2 1
V CBO
V CEO
Vcss
V CE(sat)
Collector cutoff current
(IE = 0)
Collector cutoff current
(I B = 0)
Input offset current
Collector-base voltage
(IE = 0)
Collector-emitter
voltage (lB = 0)
Collector-substrate
voltage (Icss= 0)
Collector-emitter
saturation voltage
V CB= 10V
V CE=10V
Ic= 1 mA
Ic = 10,.,A
Ic= 1 mA
Ic = 10,.,A
Ic= 10mA
V CE= 3V
IB= 1 mA
0.002
40
nA 1
see 0.5 ,.,A 2
curve
0.3 2 ,.,A 7
20 60
V-
15 24
V-
20 60
V-
0.23
V-
272





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