Single-chip Microcontroller. MN101CF97D Datasheet

MN101CF97D Microcontroller. Datasheet pdf. Equivalent


Part MN101CF97D
Description 8-bit Single-chip Microcontroller
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Manufacture Panasonic
Datasheet
Download MN101CF97D Datasheet

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MN101CF97D
MN101C97 Sriese
8-bit Single-chip Microcontroller
Overview
The MN101C series of 8-bit single-chip microcomputers incorporate multiple types of peripheral functions.
This chip series is well suited for camera, VCR, MD, TV, CD, LD, printer, telephone, home automation, pager, air conditioner, PPC, remote
control, fax machine, music instrument and other applications.
This LSI brings to embedded microcomputer applications exible, optimized hardware congurations and a simple efcient instruction
set. The MN101C97D has an internal 64 KB of ROM and 1 KB of RAM. Peripheral functions include 7 external interrupts, 13 internal
interrupts including NMI, 8 timer counters, 2 sets of serial interfaces, A/D converter, watchdog timer, buzzer output, and remote control
output. The conguration of this microcomputer is well suited for application as a system controller in a camera, timer selector for VCR, CD
player, or MD.
With two oscillation system (max. 8 MHz/32 kHz) contained on the chip, the system clock can be switched to high frequency input (high
speed mode), or to low frequency input (low speed mode).
The system clock is generated by dividing the oscillation clock. The best operation clock for the system can be selected by switching its
frequency by software. High speed mode has the normal mode which is based on 2-cycle clock (fosc/2) and the double speed mode which is
based on the same cycle clock with fosc.
A machine cycle (min. instructions execution) in the normal mode is 250 ns when fosc is 8 MHz, and when fosc is 4 MHz, a machine
cycle is 500 ns. A machine cycle in the double speed mode is 125 ns when fosc is 8 MHz, and 250 ns when fosc is 4 MHz. The package are
48-pin TQFP and 44-pin QFP.
Product Summary
This datasheet describes the following model of MN101C97 series. These products have identical function.
However, MN101C97D is described mainly.
Model
MN101C97A
MN101C97D
MN101CF97D
ROM Size
32 KB
64 KB
64 KB
RAM Size
1 KB
Classication
Mask ROM version
1 KB
Mask ROM version
1 KB
Flash EEPROM version
Package
QFP044-P-1010F
TQFP048-P-0707B
QFP044-P-1010F
TQFP048-P-0707B
QFP044-P-1010F
TQFP048-P-0707B
Publication date: January 2011
Ver. JEM
1



MN101CF97D
MN101C97 Series
Features
ROM Size:
MN101C97D, MN101CF97D
MN101C97A
65536 × 8 bit
32768 × 8 bit
RAM Size: 1024 × 8 bit
Package:
TQFP48 (7mm square, 0.5mm pitch)
QFP44 (10mm square, 0.8mm pitch) *Under planning
Machine Cycle:
<Mask ROM version MN101C97A / MN101C97D>
High speed mode <fs = fosc / 1>
0.125 ms / 8 MHz (2.7 V to 3.6 V)
0.250 ms / 4 MHz (1.8 V to 3.6 V)
High speed mode <fs = fosc / 2>
0.250 ms / 8 MHz (2.2 V to 3.6 V)
0.500 ms / 4 MHz (1.8 V to 3.6 V)
Low speed mode <fs = fx / 2>
62.5 ms / 32 kHz (1.8 V to 3.6 V)
<Flash EEPROM version MN101CF97D>
High speed mode <fs = fosc / 1>
0.250 ms / 4 MHz (2.2 V to 3.6 V)
0.270 ms / 3.7 MHz (2.0 V to 3.6 V)
0.500 ms / 2 MHz (1.8 V to 3.6 V)
High speed mode <fs = fosc / 2>
0.250 ms / 8 MHz (2.2 V to 3.6 V)
0.500 ms / 4 MHz (1.8 V to 3.6 V)
Low speed mode <fs = fx / 2>
62.5 ms / 32 kHz (1.8 V to 3.6 V)
Clock Gear Circuit Embedded:
The operation speed of system clock can be changed by switching the dividing ratio of the oscillation clock.
(1, 2, 4, 8, 16, 32, 64, 128 dividing)
Oscillation Circuit:
2 channels oscillation circuits (High-speed / Low-speed)
Operation Modes:
NORMAL mode (High-speed mode)
SLOW mode (Low-speed mode)
HALT mode (High-speed / Low-speed mode)
STOP mode
The operation clock can be switched in each mode.
ROM Correction:
Maximum of 3 parts in a program
Operation Voltage: 1.8 V to 3.6 V
Operation Temperature: -40°C to + 85°C
2 Ver. JEM





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