Flash Memory. AT49BV4096A Datasheet

AT49BV4096A Datasheet PDF, Equivalent


Part Number

AT49BV4096A

Description

4-Megabit (512K x 8/256K x 16) CMOS Flash Memory

Manufacture

ATMEL

Total Page 15 Pages
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Download AT49BV4096A Datasheet PDF


AT49BV4096A Datasheet
Features
2.7V to 3.6V Read/Write Operation
Fast Read Access Time - 120 ns
Internal Erase/Program Control
Sector Architecture
– One 8K Words (16K bytes) Boot Block with Programming Lockout
– Two 4K Words (8K bytes) Parameter Blocks
– One 240K Words (480K bytes) Main Memory Array Block
Fast Sector Erase Time - 10 seconds
Byte-by-Byte or Word-By-Word Programming - 30 µs Typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Low-Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49BV004(T) and AT49BV4096A(T) are 3-volt, 4-megabit Flash Memories
organized as 524,288 words of 8 bits each or 256K words of 16 bits each. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access
times to 120 ns with power dissipation of just 67 mW at 2.7V read. When deselected,
the CMOS standby current is less than 50 µA.
The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT49BV004/4096A locates the boot block at lowest
order addresses (“bottom boot”); the AT49BV004T/4096AT locates it at highest order
addresses (“top boot”).
To allow for simple in-system reprogrammability, the AT49BV004(T)/4096A(T) does
not require high input voltages for programming. Reading data out of the device is
similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid
bus contention. Reprogramming the AT49BV004(T)/4096A(T) is performed by first
erasing a block of data and then programming on a byte-by-byte or word-by-word
basis.
Pin Configurations
(continued)
Pin Name
A0 - A18
CE
OE
WE
RESET
RDY/BUSY
VPP
I/O0 - I/O14
I/O15(A-1)
BYTE
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Ready/Busy Output
Optional Power Supply for Faster
Program/Erase Operations
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
4-Megabit
(512K x 8/
256K x 16)
CMOS Flash
Memory
AT49BV004
AT49BV004T
AT49BV4096A
AT49BV4096AT
Preliminary
Rev. 1139A–09/98
1

AT49BV4096A Datasheet
ATBV4096A(T) SOIC (SOP)
*NC/VPP
NC
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 RESET
43 WE
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE
32 GND
31 I/O15/A-1
30 I/O7
29 I/O14
28 I/O6
27 I/O13
26 I/O5
25 I/O12
24 I/O4
23 VCC
AT49BV4096A(T) TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
*NC/VPP
NC
NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 A16
47 BYTE
46 GND
45 I/O15 / A-1
44 I/O7
43 I/O14
42 I/O6
41 I/O13
40 I/O5
39 I/O12
38 I/O4
37 VCC
36 I/O11
35 I/O3
34 I/O10
33 I/O2
32 I/O9
31 I/O1
30 I/O8
29 I/O0
28 OE
27 GND
26 CE
25 A0
*Standard device is a NC. Please contact Atmel for VPP option.
AT49BV004(T) TSOP Top View
Type 1
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
*NC/VPP
RDY/BUSY
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 A17
39 GND
38 NC
37 NC
36 A10
35 I/O7
34 I/O6
33 I/O5
32 I/O4
31 VCC
30 VCC
29 NC
28 I/O3
27 I/O2
26 I/O1
25 I/O0
24 OE
23 GND
22 CE
21 A0
The device is erased by executing the erase command
sequence; the device internally controls the erase opera-
tion. The memory is divided into four blocks for erase oper-
ations. There are two 4K word parameter block sections,
the boot block, and the main memory array block. The typi-
cal number of program and erase cycles is in excess of
10,000 cycles.
The 8K word boot block section includes a reprogramming
lock out feature to provide data integrity. This feature is
enabled by a command sequence. Once the boot block
programming lockout feature is enabled, the data in the
boot block cannot be changed when input levels of 3.6
volts or less are used. The boot sector is designed to con-
tain user secure code.
For the AT49BV4096A(T), the BYTE pin controls whether
the device data I/O pins operate in the byte or word config-
uration. If the BYTE pin is set at a logic “1” or left open, the
device is in word configuration, I/O0 - I/O15 are active and
controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte con-
figuration, and only data I/O pins I/O0 - I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8 - I/O14
are tri-stated and the I/O15 pin is used as an input for the
LSB (A-1) address function.
An optional VPP pin is available to improve program/erase
times. Please contact Atmel for more information.
2 AT49BV004(T)/4096A(T)


Features Datasheet pdf Features • 2.7V to 3.6V Read/Write Ope ration • Fast Read Access Time - 120 ns • Internal Erase/Program Control Sector Architecture – One 8K Words (16K bytes) Boot Block with Programmin g Lockout – Two 4K Words (8K bytes) P arameter Blocks – One 240K Words (480 K bytes) Main Memory Array Block • Fa st Sector Erase Time - 10 seconds • B yte-by-Byte or Word-By-Word Programming - 30 µs Typical • Hardware Data Pro tection • DATA Polling For End Of Pro gram Detection • Low-Power Dissipatio n – 25 mA Active Current – 50 µA C MOS Standby Current • Typical 10,000 Write Cycles Description The AT49BV00 4(T) and AT49BV4096A(T) are 3-volt, 4-m egabit Flash Memories organized as 524, 288 words of 8 bits each or 256K words of 16 bits each. Manufactured with Atme l’s advanced nonvolatile CMOS technol ogy, the devices offer access times to 120 ns with power dissipation of just 6 7 mW at 2.7V read. When deselected, the CMOS standby current is less than 50 µA. The device contains.
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