Flash Memory. Am29DL400B Datasheet

Am29DL400B Memory. Datasheet pdf. Equivalent

Am29DL400B Datasheet
Recommendation Am29DL400B Datasheet
Part Am29DL400B
Description 4 Megabit CMOS 3.0 Volt-only Simultaneous Operation Flash Memory
Feature Am29DL400B; Am29DL400B 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash.
Manufacture AMD
Datasheet
Download Am29DL400B Datasheet




AMD Am29DL400B
Am29DL400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
s Simultaneous Read/Write operations
— Host system can program or erase in one bank,
then immediately and simultaneously read from
the other bank
— Zero latency between read and write operations
— Read-while-erase
— Read-while-program
s Single power supply operation
— 2.7 to 3.6 volt read and write operations for
battery-powered applications
s Manufactured on 0.32 µm process technology
s High performance
— Access times as fast as 70 ns
s Low current consumption (typical values
at 5 MHz)
— 7 mA active read current
— 21 mA active read-while-program or read-while-
erase current
— 17 mA active program-while-erase-suspended
current
— 200 nA in standby mode
— 200 nA in automatic sleep mode
— Standard tCE chip enable access time applies to
transition from automatic sleep mode to active mode
s Flexible sector architecture
— Two 16 Kword, two 8 Kword, four 4 Kword, and
six 32 Kword sectors in word mode
— Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and
six 64 Kbyte sectors in byte mode
— Any combination of sectors can be erased
— Supports full chip erase
s Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
s Sector protection
— Hardware method of locking a sector to prevent
any program or erase operation within that
sector
— Sectors can be locked in-system or via
programming equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s Top or bottom boot block configurations available
s Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases sectors or entire chip
— Embedded Program algorithm automatically
programs and verifies data at specified address
s Minimum 1 million program/erase cycles
guaranteed per sector
s 20-year data retention at 125° C
— Reliable operation for the life of the system
s Package options
— 44-pin SO
— 48-pin TSOP
s Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
— Superior inadvertent write protection
s Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
s Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or
erase cycle completion
s Erase Suspend/Erase Resume
— Suspends or resumes erasing sectors to allow
reading and programming in other sectors
— No need to suspend if sector is in the other bank
s Hardware reset pin (RESET#)
— Hardware method of resetting the device to
reading array data
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21606 Rev: E Amendment/+2
Issue Date: November 21, 2000



AMD Am29DL400B
GENERAL DESCRIPTION
The Am29DL400B is an 4 Mbit, 3.0 volt-only flash
memory device, organized as 262,144 words or
524,288 bytes. The device is offered in 44-pin SO and
48-pin TSOP packages. The word-wide (x16) data ap-
pears on DQ0–DQ15; the byte-wide (x8) data appears
on DQ0–DQ7. This device requires only a single 3.0
volt VCC supply to perform read, program, and erase
operations. A standard EPROM programmer can also
be used to program and erase the device.
The standard device offers access times of 70, 80, 90,
and 120 ns, allowing high-speed microprocessors to
operate without wait states. Standard control pins—
chip enable (CE#), write enable (WE#), and output en-
able (OE#)—control read and write operations, and
avoid bus contention issues.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides si-
multaneous operation by dividing the memory space
into two banks. Bank 1 contains boot/parameter sec-
tors, and Bank 2 consists of larger, code sectors of
uniform size. The device can improve overall system
performance by allowing a host system to program or
erase in one bank, then immediately and simulta-
neously read from the other bank, with zero latency.
This releases the system from waiting for the comple-
tion of program or erase operations.
Am29DL400B Features
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command reg-
ister using standard microprocessor write timings.
Register contents serve as input to an internal state
machine that controls the erase and programming cir-
cuitry. Write cycles also internally latch addresses and
data needed for the programming and erase opera-
tions. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device automatically returns to
reading array data.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
or y. This can be achieved i n-system or via
programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector within that bank that is
not selected for erasure. True background erase can
thus be achieved. There is no need to suspend the
erase operation if the read data is in the other bank.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device to reading array data, enabling the sys-
tem microprocessor to read the boot-up firmware from
the Flash memory.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
hi g h e st leve l s o f q u a li ty, r e li a bi li t y, a n d co s t
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte or word
at a time using hot electron injection.
2 Am29DL400B



AMD Am29DL400B
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29DL400B Device Bus Operations ................................9
Word/Byte Configuration .......................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Simultaneous Read/Write Operations with Zero Latency ....... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 11
Table 2. Am29DL400BT Top Boot Sector Architecture ..................11
Table 3. Am29DL400BB Bottom Boot Sector Architecture .............12
Autoselect Mode ..................................................................... 12
Table 4. Am29DL400B Autoselect Codes (High Voltage Method) ..13
Sector Protection/Unprotection ............................................... 13
Temporary Sector Unprotect .................................................. 13
Figure 1. Temporary Sector Unprotect Operation........................... 13
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 14
Hardware Data Protection ...................................................... 15
Low VCC Write Inhibit ............................................................ 15
Write Pulse “Glitch” Protection ............................................... 15
Logical Inhibit .......................................................................... 15
Power-Up Write Inhibit ............................................................ 15
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 15
Reading Array Data ................................................................ 15
Reset Command ..................................................................... 15
Autoselect Command Sequence ............................................ 15
Byte/Word Program Command Sequence ............................. 16
Unlock Bypass Command Sequence ..................................... 16
Figure 3. Program Operation .......................................................... 17
Chip Erase Command Sequence ........................................... 17
Sector Erase Command Sequence ........................................ 17
Erase Suspend/Erase Resume Commands ........................... 18
Figure 4. Erase Operation............................................................... 18
Command Definitions ............................................................. 19
Table 5. Am29DL400B Command Definitions ................................19
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 20
DQ7: Data# Polling ................................................................. 20
Figure 5. Data# Polling Algorithm ................................................... 20
RY/BY#: Ready/Busy# ........................................................... 21
DQ6: Toggle Bit I .................................................................... 21
DQ2: Toggle Bit II ................................................................... 21
Reading Toggle Bits DQ6/DQ2 ............................................... 21
Figure 6. Toggle Bit Algorithm........................................................ 22
DQ5: Exceeded Timing Limits ................................................ 22
DQ3: Sector Erase Timer ....................................................... 22
Table 6. Write Operation Status ..................................................... 23
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 24
Figure 7. Maximum Negative Overshoot Waveform ..................... 24
Figure 8. Maximum Positive Overshoot Waveform....................... 24
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 26
Figure 10. Typical ICC1 vs. Frequency ........................................... 26
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Test Setup.................................................................... 27
Table 7. Test Specifications ........................................................... 27
Key to Switching Waveforms .................................................. 27
Figure 12. Input Waveforms and Measurement Levels ................. 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13. Read Operation Timings ............................................... 28
Figure 14. Reset Timings ............................................................... 29
Figure 15. BYTE# Timings for Read Operations............................ 30
Figure 16. BYTE# Timings for Write Operations............................ 30
Figure 17. Program Operation Timings.......................................... 32
Figure 18. Chip/Sector Erase Operation Timings .......................... 32
Figure 19. Back-to-Back Read/Write Cycle Timings ...................... 33
Figure 20. Data# Polling Timings (During Embedded Algorithms). 33
Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 34
Figure 22. DQ2 vs. DQ6................................................................. 34
Figure 23. Temporary Sector Unprotect Timing Diagram .............. 35
Figure 24. Sector Protect/Unprotect Timing Diagram .................... 36
Figure 25. Alternate CE# Controlled Erase/Program
Operation Timings.......................................................................... 38
Erase and Programming Performance . . . . . . . 39
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 39
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 39
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40
TS 048—48-Pin Standard TSOP ............................................... 40
TSR048—48-Pin Reverse TSOP .............................................. 41
SO 044—44-Pin Small Outline .................................................. 42
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision A (January 1998) ..................................................... 43
Revision B (March 1998) ........................................................ 43
Revision C (April 1998) ........................................................... 43
Revision D (June 1999) .......................................................... 43
Revision D+1 (March 23, 1999) .............................................. 43
Revision E (December 7, 1999) .............................................. 43
Revision E+1 (May 12, 2000) ................................................. 43
Am29DL400B
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