AT40K FPGA. AT94K10AL Datasheet

AT94K10AL Datasheet PDF, Equivalent


Part Number

AT94K10AL

Description

5K - 40K Gates of AT40K FPGA

Manufacture

ATMEL

Total Page 30 Pages
PDF Download
Download AT94K10AL Datasheet


AT94K10AL Datasheet
Features
Monolithic Field Programmable System Level Integrated Circuit (FPSLIC®)
– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR® Core,
Extensive Data and Instruction SRAM and JTAG ICE
5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM
– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
– High-performance DSP Optimized FPGA Core Cell
– Dynamically Reconfigurable In-System – FPGA Configuration Access Available
On-chip from AVR Microcontroller Core to Support Cache Logic® Designs
– Very Low Static and Dynamic Power Consumption – Ideal for Portable and
Handheld Applications
Patented AVR Enhanced RISC Architecture
– 120+ Powerful Instructions – Most Single Clock Cycle Execution
– High-performance Hardware Multiplier for DSP-based Systems
– Approaching 1 MIPS per MHz Performance
– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
– Low-power Idle, Power-save and Power-down Modes
– 100 µA Standby and Typical 2-3 mA per MHz Active
Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
JTAG (IEEE std. 1149.1 Compliant) Interface
– Extensive On-chip Debug Support
– Limited Boundary-scan Capabilities According to the JTAG Standard (AVR Ports)
AVR Fixed Peripherals
– Industry-standard 2-wire Serial Interface
– Two Programmable Serial UARTs
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9- or 10-bit PWM
Support for FPGA Custom Peripherals
– AVR Peripheral Control – 16 Decoded AVR Address Lines Directly Accessible
to FPGA
– FPGA Macro Library of Custom Peripherals
16 FPGA Supplied Internal Interrupts to AVR
Up to Four External Interrupts to AVR
8 Global FPGA Clocks
– Two FPGA Clocks Driven from AVR Logic
– FPGA Global Clock Access Available from FPGA Core
Multiple Oscillator Circuits
– Programmable Watchdog Timer with On-chip Oscillator
– Oscillator to AVR Internal Clock Circuit
– Software-selectable Clock Frequency
– Oscillator to Timer/Counter for Real-time Clock
VCC: 3.0V - 3.6V
3.3V 33 MHz PCI-compliant FPGA I/O
– 20 mA Sink/Source High-performance I/O Structures
– All FPGA I/O Individually Programmable
High-performance, Low-power 0.35µ CMOS Five-layer Metal Process
State-of-the-art Integrated PC-based Software Suite including Co-verification
5V I/O Tolerant
Green (Pb/Halide-free/ROHS compliant) Package Options Available
5K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller,
up to 36K Bytes
of SRAM and
On-chip
JTAG ICE
AT94KAL Series
Field
Programmable
System Level
Integrated
Circuit
1138I–FPSLI–1/08

AT94K10AL Datasheet
1. Description
The AT94KAL Series FPSLIC family shown in Table 1-1 is a combination of the popular Atmel
AT40K Series SRAM FPGAs and the high-performance Atmel AVR 8-bit RISC microcontroller
with standard peripherals. Extensive data and instruction SRAM as well as device control and
management logic are included on this monolithic device, fabricated on Atmel’s 0.35µ five-layer
metal CMOS process.
The AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA with distributed
10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks,
Cache Logic ability (partially or fully reconfigurable without loss of data) and 5,000 to 40,000
usable gates.
Table 1-1. The AT94K Series Characteristics
Device
AT94K05AL
FPGA Gates
5K
FPGA Core Cells
256
FPGA SRAM Bits
2048
FPGA Registers (Total)
436
Maximum FPGA User I/O
96
AVR Programmable I/O
Lines
8
Program SRAM
4 Kbytes - 16 Kbytes
Data SRAM
Hardware Multiplier (8-bit)
2-wire Serial Interface
UARTs
Watchdog Timer
Timer/Counters
Real-time Clock
JTAG ICE
Typical AVR
throughput
@ 25
MHz
Operating Voltage
4 Kbytes - 16 Kbytes
Yes
Yes
2
Yes
3
Yes
Yes(1)
19 MIPS
3.0 - 3.6V
AT94K10AL
10K
576
4096
846
116
16
20 Kbytes - 32
Kbytes
4 Kbytes- 16 Kbytes
Yes
Yes
2
Yes
3
Yes
Yes(1)
19 MIPS
3.0 - 3.6V
AT94K40AL
40K
2304
18432
2862
120
16
20 Kbytes - 32
Kbytes
4 Kbytes - 16 Kbytes
Yes
Yes
2
Yes
3
Yes
Yes(1)
19 MIPS
3.0 - 3.6V
Notes: 1. FPSLIC parts with JTAG ICE support can be identified by the letter “J” after the device date
code, e.g., 4201 (no ICE support) and 4201J (with ICE support), see Figure 1-1.
2 AT94KAL Series FPSLIC
1138I–FPSLI–1/08


Features Datasheet pdf Features • Monolithic Field Programmab le System Level Integrated Circuit (FPS LIC®) – AT40K SRAM-based FPGA with E mbedded High-performance RISC AVR® Cor e, Extensive Data and Instruction SRAM and JTAG ICE • 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM™ – 2 - 18.4 Kbits of Distri buted Single/Dual Port FPGA User SRAM High-performance DSP Optimized FPGA Core Cell – Dynamically Reconfigurabl e In-System – FPGA Configuration Acce ss Available On-chip from AVR Microcont roller Core to Support Cache Logic® De signs – Very Low Static and Dynamic P ower Consumption – Ideal for Portable and Handheld Applications • Patented AVR Enhanced RISC Architecture – 120 + Powerful Instructions – Most Single Clock Cycle Execution – High-perform ance Hardware Multiplier for DSP-based Systems – Approaching 1 MIPS per MHz Performance – C Code Optimized Archit ecture with 32 x 8 General-purpose Inte rnal Registers – Low-power Idle, Power-save and Power-down Mo.
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