Synchronous Up/Down Decade Counter (Single Clock Line)
Synchronous Up/Down 4-bit Binary Counter (Single Clock Line)
Jan 31, 2006
The HD74HC190 is a 4-bit decade counter and the HD74HC191 is a 4-bit binary counter. Synchronous counting
operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each
other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally
associated with asynchronous (ripple clock) counters.
The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if the Enable G input
is low. A high at Enable G inhibits counting. The direction of the count is determined by the level of the Down/ Up
(D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down.
These counters feature a fully independent clock circuit. Changes at the control inputs (D/U) that will modify the
operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter will be
dictated solely by the condition meeting the stable setup and hold times.
These counters are fully programmable; that is, the outputs may each be preset to either level by placing a low on the
load input and entering the desired data at the data inputs. The output will change to agree with the data inputs
independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by
simply modifying the count length with the preset inputs.
Two outputs have been made available to perform the cascading function. Ripple clock and maximum/minimum count.
The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the
clock while the count is zero (all outputs low) counting down or maximum (9 or 15) counting up. The ripple clock
output produces a low-level output pulse under those same conditions but only while the clock input is low. The
counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if
parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be
used to accomplish look-ahead for high-speed operation.
• High Speed Operation: tpd (Clock to Q) = 22 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
SOP-16 pin (JEITA)
SOP-16 pin (JEDEC)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Rev.3.00, Jan 31, 2006 page 1 of 12