8-Bit Parallel-Out Serial-in Shift Register
This 8-bit shift register features gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit
complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the
first flip-flop to the low level at the next clock pulse. A high-level input enables the other input which will them
determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but
only information meeting the setup requirements will be entered. Clocking occurs on the low-to-high-level transition of
the clock input.
• Ordering Information
HD74LS164FPEL SOP-14 pin (JEITA)
HD74LS164RPEL SOP-14 pin (JEDEC)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
QD CK CLR
Rev.2.00, Feb.18.2005, page 1 of 8