CMOS EEPROM. IS24C32B Datasheet

IS24C32B EEPROM. Datasheet pdf. Equivalent


ISSI IS24C32B
IS24C32A/B
IS24C64A/B
ISSI®
65,536 bit/32,768 bit
2-WIRE SERIAL CMOS EEPROM
ADVANCED INFORMATION
MAY 2004
FEATURES
• Two-Wire Serial Interface
–Bi-directional data transfer protocol
• 400 KHz (I2C Protocol) Compatibility
• Low Power CMOS Technology
–Standby Current less than 6 µA (5.0V)
–Read Current less than 2 mA (5.0V)
–Write Current less than 3 mA (5.0V)
• Flexible Voltage Operation
–Vcc = 1.8V to 5.5V for –2 version
–Vcc = 2.5V to 5.5V for –3 version
• Hardware Data Protection
–IS24C32A/64A: WP protects entire array
–IS24C32B/64B: WP protects top quarter of
array
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• 8-pin PDIP, 8-pin SOIC and 8-pin TSSOP
packages
• Self time write cycle with auto clear
5 ms @ 2.5V
• Organization:
–IS24C32A/B: 4Kx8 (128 pages of 32 bytes)
–IS24C64A/B: 8Kx8 (256 pages of 32 bytes)
• 32 Byte Page Write Buffer
• High Reliability
–Endurance: 1,000,000 Cycles
–Data Retention: 100 Years
• Commercial and Industrial temperature ranges
DESCRIPTION
The IS24C32A/B and IS24C64A/B are electrically
erasable PROM devices that use the standard 2-
wire interface for communications. The IS24C32A/B
and IS24C64A/B contain a memory array of 32K-
bits (4K x 8) and 64K-bits (8K x 8), respectively.
Each device is organized into 32 byte pages for
page write mode.
This EEPROM is offered in wide operating volt-
ages of 1.8V to 5.5V (IS24Cxx-2) and 2.5V to 5.5V
(IS24Cxx-3) to be compatible with most application
voltages. ISSI designed this device family to be a
practical, low-power 2-wire EEPROM solution.
The devices are available in 8-pin PDIP, 8-pin
SOIC and 8-pin TSSOP packages.
The IS24C32A/32B/64A/64B (IS24CXX) maintains
compatibility with the popular 2-wire bus protocol,
so it is easy to use in applications implementing
this bus type. The simple bus consists of the
Serial Clock wire (SCL) and the Serial Data wire
(SDA). Using the bus, a Master device such as a
microcontroller is usually connected to one or
more Slave devices such as this device. The bit
stream over the SDA line includes a series of
bytes, which identifies a particular Slave device,
an instruction, an address within that Slave device,
and a series of data, if appropriate. The IS24CXX
has a Write Protect pin (WP) to allow blocking of
any write instruction transmitted over the bus.
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00B
05/05/04
1


IS24C32B Datasheet
Recommendation IS24C32B Datasheet
Part IS24C32B
Description 2-WIRE SERIAL CMOS EEPROM
Feature IS24C32B; IS24C32A/B IS24C64A/B ISSI® 65,536 bit/32,768 bit 2-WIRE SERIAL CMOS EEPROM ADVANCED INFORMATION .
Manufacture ISSI
Datasheet
Download IS24C32B Datasheet




ISSI IS24C32B
IS24C32A/B
IS24C64A/B
FUNCTIONAL BLOCK DIAGRAM
Vcc 8
SDA 5
SCL 6
WP 7
A0 1
A1 2
A2 3
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
WORD ADDRESS
COUNTER
GND 4
nMOS
ACK
ISSI ®
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
EEPROM
ARRAY
Y
DECODER
Clock
DI/O
> DATA
REGISTER
PIN DESCRIPTIONS
A0-A2
SDA
SCL
WP
Vcc
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire-Ored with other open drain
or open collector outputs. The SDA bus requires a pullup
resistor to Vcc.
A0, A1, A2
The A0, A1 and A2 are the device address inputs that are
hardwired or left not connected for hardware compatibility
with the 24C16. When pins are hardwired, as many as eight
32K/64K devices may be addressed on a single bus
system. When the pins are not hardwired, the default values
of A0, A1, and A2 are zero.
PIN CONFIGURATION
8-Pin DIP, SOIC, and TSSOP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
WP
WP is the Write Protect pin. The input level determines if all,
partial, or none of the array is protected from modifications.
Write Protection
Array Addresses Protected
WP
GND or floating
Vcc
IS24C32A/64A
None
Entire Array
IS24C32B
None
C00h
-FFFh
IS24C64B
None
1800h
-1FFFh
2 Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00B
05/05/04



ISSI IS24C32B
IS24C32A/B
IS24C64A/B
ISSI ®
DEVICE OPERATION
IS24CXX features serial communication and supports a bi-
directional 2-wire bus transmission protocol.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the
receiving devices as a receiver. The bus is controlled by a
Master device that generates the SCL, controls the bus
access, and generates the Stop and Start conditions. The
IS24CXX is the Slave device on the bus.
The Bus Protocol:
– Data transfer may be initiated only when the bus is not
busy
– During a data transfer, the data line must remain stable
whenever the clock line is high. Any changes in the data
line while the clock line is high will be interpreted as a
Start or Stop condition.
The state of the data line represents valid data after a Start
condition. The data line must be stable for the duration of the
High period of the clock signal. The data on the SDA line
may be changed during the Low period of the clock signal.
There is one clock pulse per bit of data. Each data transfer
is initiated with a Start condition and terminated with a Stop
condition.
Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when SCL
is High. The EEPROM monitors the SDA and SCL lines and
will not respond until the Start condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition of
SDA when SCL is High. All operations must end with a Stop
condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The IS24CXX contains a reset function in case the 2-
wire bus transmission is accidentally interrupted (eg. a
power loss), or needs to be terminated mid-stream. The
reset is caused when the Master device creates a Start
condition. To do this, it may be necessary for the Master
device to monitor the SDA line, which may cycle the
SCL up to nine times. (For each clock signal transition to
High, the Master checks for a High level on SDA.)
Standby Mode
Power consumption is reduced in standby mode. The
IS24CXX will enter standby mode: a) At Power-up, and
remain in it until SCL or SDA toggles; b) Following the Stop
signal if a no write operation is initiated; or c) Following any
internal write operation.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00B
05/05/04
3







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