Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
During normal operation, these (and other) reverse-
biased ESD diodes leak, forming the only current drawn
from V+ or V-.
Virtually all the analog leakage current comes from the
ESD diodes. Although the ESD diodes on a given signal
pin are identical, and therefore fairly well balanced,
they are reverse biased differently. Each is biased by
either V+ or V- and the analog signal. This means their
leakages will vary as the signal varies. The difference in
the two diode leakages to the V+ and V- pins consti-
tutes the analog signal path leakage current. All analog
leakage current flows between each pin and one of the
supply terminals, not to the other switch terminal. This is
why both sides of a given switch can show leakage cur-
rents of either the same or opposite polarity.
V+ and GND power the internal logic and logic-level
translators, and set both the input and output logic lim-
its. The logic-level translators convert the logic levels
into switched V+ and V- signals to drive the gates of the
analog signals. This drive signal is the only connection
between the logic supplies (and signals) and the ana-
log supplies. V+ and V- have ESD-protection diodes on
The MAX4691/MAX4692/MAX4693 operate with bipolar
supplies between ±2V and ±5.5V. The V+ and V- sup-
plies need not be symmetrical, but their difference can-
not exceed the absolute maximum rating of +12V.
These devices operate from a single supply between +2V
and +11V when V- is connected to GND. All of the bipolar
precautions must be observed. At room temperature,
they operate with a single supply at near or below +2V,
although as supply voltage decreases, switch on-resis-
tance and switching times become very high.
Always bypass supplies with a 0.1µF capacitor.
Proper power-supply sequencing is recommended for
all CMOS devices. Do not exceed the absolute maxi-
mum ratings, because stresses beyond the listed rat-
ings can cause permanent damage to the devices.
Always sequence V+ on first, then V-, followed by the
logic inputs and by W, X, Y, Z. If power-supply
sequencing is not possible, add two small signal
diodes (D1, D2) in series with the supply pins for over-
voltage protection (Figure 1).
Adding diodes reduces the analog signal range to one
diode drop below V+ and one diode drop above V-, but
does not affect the devices’ low switch resistance and
low leakage characteristics. Device operation is
unchanged, and the difference between V+ and V-
should not exceed 12V. These protection diodes are
not recommended when using a single supply if signal
levels must extend to ground.
The chip-scale package (UCSP) represents a unique
package that greatly reduces board space compared to
other packages. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review these
areas when considering a UCSP. Performance through
Operating Life Test and Moisture Resistance is equal to
conventional package technology as it is primarily deter-
mined by the wafer-fabrication process. However, this
form factor may not perform equally to a packaged prod-
uct through traditional mechanical reliability tests.
Mechanical stress performance is a greater considera-
tion for a UCSP. UCSP solder joint contact integrity
must be considered since the package is attached
through direct solder contact to the user’s PC board.
Testing done to characterize the UCSP reliability per-
formance shows that it is capable of performing reli-
ably through environmental stresses. Results of
environmental stress tests and additional usage data
and recommendations are detailed in the UCSP appli-
cation note, which can be found on Maxim’s website,
EXTERNAL BLOCKING DIODE
EXTERNAL BLOCKING DIODE
V- (GND )
*INTERNAL PROTECTION DIODES
( ) ARE FOR THE MAX4694 ONLY, REPLACE V- WITH GND.
Figure 1. Overvoltage Protection