In-System-Programmable Peripherals. PSD4135G2 Datasheet


PSD4135G2 Peripherals. Datasheet pdf. Equivalent


PSD4135G2


Flash In-System-Programmable Peripherals
PSD4135G2
Flash In-System-Programmable Peripherals for 16-Bit MCUs
PRELIMINARY DATA

FEATURES SUMMARY s 5 V±10% Single Supply Voltage: s Up to 4 Mbit of Primary Flash Memory (8
uniform sectors) s 256Kbit Secondary Flash Memory (4 uniform
sectors) s Up to 64 Kbit SRAM s Over 3,000 Gates of PLD: DPLD and CPLD s 52 Reconfigurable I/O ports s Enhanced JTAG Serial Port s Programmable power management s High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory – 1,000 Erase/Write Cycles of PLD

Figure 1. Packages
TQFP80 (U)

January 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1/3

PSD4000 Series
PSD4135G2 Flash In-System-Programmable Peripherals for 16-Bit MCUs
Table of Contents
Introduction ........................................................................................................................................................................................1 In-System...



PSD4135G2
PSD4135G2
Flash In-System-Programmable Peripherals
for 16-Bit MCUs
PRELIMINARY DATA
FEATURES SUMMARY
s 5 V±10% Single Supply Voltage:
s Up to 4 Mbit of Primary Flash Memory (8
uniform sectors)
s 256Kbit Secondary Flash Memory (4 uniform
sectors)
s Up to 64 Kbit SRAM
s Over 3,000 Gates of PLD: DPLD and CPLD
s 52 Reconfigurable I/O ports
s Enhanced JTAG Serial Port
s Programmable power management
s High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 1,000 Erase/Write Cycles of PLD
Figure 1. Packages
TQFP80 (U)
January 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/3

PSD4135G2
PSD4000 Series
PSD4135G2
Flash In-System-Programmable Peripherals for 16-Bit MCUs
Table of Contents
Introduction ........................................................................................................................................................................................1
In-System Programming (ISP) JTAG .......................................................................................................................................2
In-Application re-Programming (IAP) .......................................................................................................................................2
Key Features......................................................................................................................................................................................3
PSD4000 Family ................................................................................................................................................................................3
Block Diagram....................................................................................................................................................................................4
Architectural Overview .......................................................................................................................................................................5
Memory ....................................................................................................................................................................................5
PLDs.........................................................................................................................................................................................5
I/O Ports ...................................................................................................................................................................................5
Microcontroller Bus Interface....................................................................................................................................................5
ISP via JTAG Port ....................................................................................................................................................................6
In-System Programming (ISP) .................................................................................................................................................6
In-Application re-Programming (IAP) .......................................................................................................................................6
Page Register...........................................................................................................................................................................6
Power Management Unit ..........................................................................................................................................................6
Development System .........................................................................................................................................................................7
Pin Descriptions .................................................................................................................................................................................8
Register Description and Address Offset .........................................................................................................................................11
Register Bit Definition ......................................................................................................................................................................12
Functional Blocks .............................................................................................................................................................................15
Memory Blocks .......................................................................................................................................................................15
Main Flash and Secondary Flash Memory Description ...................................................................................................15
SRAM...............................................................................................................................................................................26
Memory Select Signals ....................................................................................................................................................26
Page Register ..................................................................................................................................................................29
Memory ID Registers .......................................................................................................................................................30
PLDs.......................................................................................................................................................................................31
Decode PLD (DPLD)........................................................................................................................................................33
General Purpose PLD (GPLD).........................................................................................................................................33
Microcontroller Bus Interface..................................................................................................................................................36
Interface to a Multiplexed Bus..........................................................................................................................................36
Interface to a Non-multiplexed Bus ..................................................................................................................................36
Data Byte Enable Reference ...........................................................................................................................................38
Microcontroller Interface Examples..................................................................................................................................39
I/O Ports .................................................................................................................................................................................44
General Port Architecture ................................................................................................................................................44
Port Operating Modes ......................................................................................................................................................44
Port Configuration Registers (PCRs) ...............................................................................................................................48
Port Data Registers..........................................................................................................................................................49
Ports A, B and C – Functionality and Structure ...............................................................................................................50
Port D – Functionality and Structure ................................................................................................................................51
Port E – Functionality and Structure ................................................................................................................................51
Port F – Functionality and Structure ................................................................................................................................52
Port G – Functionality and Structure ................................................................................................................................52
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