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CVSS

CMOS Gate Array

Description

&966 $0,+* PLFURQ &026 *DWH $UUD\ Description CVSS is the resistive tie-down to the core VSS bus for all cell inputs. Equivalent Gates ................... 1.0 HDL Syntax Verilog .................... CVSS inst_name (Q); VHDL...................... inst_name: CVSS port map (Q); CVSS Q ® Core Logic 3-44 ...

AMI

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