ODQTE60M Array Datasheet

ODQTE60M Datasheet, PDF, Equivalent


Part Number

ODQTE60M

Description

CMOS Gate Array

Manufacture

AMI

Total Page 2 Pages
Datasheet
Download ODQTE60M Datasheet


ODQTE60M
2'47(0
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
ODQTE60M is an enabled crystal oscillator, output driver pad piece that runs over a frequency range of 20 - 60 MHz.
QI is the input from the IDQC3. E is the oscillator high input enable. PADM is the bond pad to Xtal-out.
Logic Symbol
Logic Schematic
ODQTE60M
E
QI
PADM
QC E
P QC
D
QO
E
QI
ODQTE60M
Xtal-in
Xtal-out
Truth Table
PADM
H
H
L
E
L
H
H
QI
X
L
H
Pin Loading
Load
E 6.5 eql
QI 5.5 eql
HDL Syntax
Verilog .................... ODQTE60M inst_name (PADM, E, QI);
VHDL...................... inst_name: ODQTE60M port map (PADM, E, QI);
Power Characteristics
Parameter
Static IDD (TJ = 85°C)
EQLpd
See page 2-15 for power equation.
Value
TBD
176.1
Units
nA
Eq-load
4-33

ODQTE60M
2'47(0
®
$0,+*  PLFURQ &026 *DWH $UUD\
Propagation Delays
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Delay (ns)
From
To Parameter
15
E
PADM
tPLH
tPHL
2.78
1.53
QI
PADM
tPLH
tPHL
1.53
1.54
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
50
4.63
3.37
3.38
3.43
Capacitive Load (pF)
100
7.29
6.01
6.03
6.06
200
12.61
11.28
11.33
11.30
300 (max)
17.93
16.57
16.64
16.60
Design Notes:
The ODQTE60M is the output cell of a two cell oscillator circuit. The QI pin is to be connected the QO pin of the IDQC3 oscillator input receiver piece. Two package pins
are required to create a complete oscillator.
4-34


Features 2'47(0 ® $0,+*  PLFURQ &026 *DWH $UUD Description ODQTE60M is an enabl ed crystal oscillator, output driver pa d piece that runs over a frequency rang e of 20 - 60 MHz. QI is the input from the IDQC3. E is the oscillator high inp ut enable. PADM is the bond pad to Xtal -out. Logic Symbol Logic Schematic O DQTE60M E QI PADM QC E P QC D QO E Q I ODQTE60M Xtal-in Xtal-out Truth T able PADM H H L E L H H QI X L H Pi n Loading Load E 6.5 eql QI 5.5 eql H DL Syntax Verilog .................... ODQTE60M inst_name (PADM, E, QI); VHDL. ..................... inst_name: ODQTE6 0M port map (PADM, E, QI); Power Chara cteristics Parameter Static IDD (TJ = 8 5°C) EQLpd See page 2-15 for power equ ation. Value TBD 176.1 Units nA Eq-lo ad Pad Logic 4-33 2'47(0 ® $0, +*  PLFURQ &026 *DWH $UUD Propagati on Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Delay (ns) From To Parameter 15 E PADM tPLH tPHL 2.78 1.53 QI PADM tPLH tPHL 1.53 1.54 Delay will vary w.
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