ODTSXE24 Array Datasheet

ODTSXE24 Datasheet, PDF, Equivalent


Part Number

ODTSXE24

Description

CMOS Gate Array

Manufacture

AMI

Total Page 2 Pages
Datasheet
Download ODTSXE24 Datasheet


ODTSXE24
2'76;([[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
ODTSXExx is a family of 4 to 24 mA, non-inverting, TTL-level, tristate output buffer pieces with active low enables and
controlled slew rate outputs.
Logic Symbol
Truth Table
ODTSXExx
EN
A SL
PADM
EN A PADM
LL
L
LH H
HX
Z
HDL Syntax
Verilog .................... ODTSXExx inst_name (PADM, A, EN);
VHDL...................... inst_name: ODTSXExx port map (PADM, A, EN);
Pin Loading
Pin Name
A (eq-load)
EN (eq-load)
PADM (pF)
ODTSXE04
2.3
6.9
4.94
Power Characteristics
Cell Output Drive (mA)
ODTSXE04
4
ODTSXE08
8
ODTSXE12
12
ODTSXE16
16
ODTSXE24
24
a. See page 2-15 for power equation.
ODTSXE08
2.3
6.9
4.94
Load
ODTSXE12
2.3
6.9
4.94
ODTSXE16
2.3
6.9
4.94
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
218.9
TBD
240.3
TBD
261.1
TBD
283.9
TBD
302.7
ODTSXE24
2.3
6.9
4.94
4-38

ODTSXE24
2'76;([[
®
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Capacitive Load (pF)
15
ODTSXE04
From: A
tPLH
To: PADM tPHL
2.53
4.24
From: EN
tZH
To: PADM tZL
1.65
3.99
Capacitive Load (pF)
15
ODTSXE08
From: A
tPLH
To: PADM tPHL
1.82
2.62
From: EN
tZH
To: PADM tZL
1.46
2.53
Capacitive Load (pF)
15
ODTSXE12
From: A
tPLH
To: PADM tPHL
1.71
2.61
From: EN
tZH
To: PADM tZL
1.42
1.96
Capacitive Load (pF)
15
ODTSXE16
From: A
tPLH
To: PADM tPHL
1.73
2.15
From: EN
tZH
To: PADM tZL
1.39
1.91
Capacitive Load (pF)
15
ODTSXE24
From: A
tPLH
To: PADM tPHL
1.72
1.96
From: EN
tZH
To: PADM tZL
1.48
1.63
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
50
4.23
9.70
3.91
9.44
50
2.84
5.68
2.51
5.45
50
2.43
4.23
2.14
3.96
50
2.28
3.52
1.96
3.36
50
2.26
2.90
2.04
2.59
Tristate Timing
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Delay (ns)
From
To
EN PADM
Parameter
tHZ
tLZ
ODTSXE04
0.82
0.86
ODTSXE08
1.04
1.04
$0,+*  PLFURQ &026 *DWH $UUD\
100
7.00
17.28
6.79
16.99
100
4.27
9.82
3.97
9.54
100
3.40
6.93
3.11
6.72
100
3.02
5.54
2.70
5.34
100
3.01
4.22
2.78
3.94
200
12.66
32.07
12.31
31.78
200
7.12
17.67
6.83
17.43
200
5.32
12.29
5.03
12.01
200
4.45
9.49
4.13
9.23
200
4.45
6.84
4.22
6.58
300 (max)
18.22
46.58
18.00
46.36
300 (max)
9.98
25.18
9.65
24.94
300 (max)
7.25
17.32
6.96
17.11
300 (max)
5.85
13.31
5.55
13.16
300 (max)
5.87
9.47
5.63
9.19
Cell
ODTSXE12
1.27
1.20
ODTSXE16
1.53
1.38
ODTSXE24
1.42
1.46
4-39


Features 2'76;([[ ® $0,+*  PLFURQ &026 *DW H $UUD Description ODTSXExx is a famil y of 4 to 24 mA, non-inverting, TTL-lev el, tristate output buffer pieces with active low enables and controlled slew rate outputs. Logic Symbol Truth Tabl e ODTSXExx EN A SL PADM EN A PADM LL L LH H HX Z HDL Syntax Verilog .. .................. ODTSXExx inst_name ( PADM, A, EN); VHDL..................... . inst_name: ODTSXExx port map (PADM, A , EN); Pin Loading Pin Name A (eq-loa d) EN (eq-load) PADM (pF) ODTSXE04 2.3 6.9 4.94 Power Characteristics Cell Output Drive (mA) ODTSXE04 4 ODTSXE0 8 8 ODTSXE12 12 ODTSXE16 16 ODTSX E24 24 a. See page 2-15 for power equ ation. ODTSXE08 2.3 6.9 4.94 Load ODT SXE12 2.3 6.9 4.94 ODTSXE16 2.3 6.9 4. 94 Power Characteristicsa Static IDD (TJ = 85°C) (nA) TBD EQLpd (Eq-load) 218.9 TBD 240.3 TBD 261.1 TBD 283 .9 TBD 302.7 ODTSXE24 2.3 6.9 4.94 Pad Logic 4-38 2'76;([[ ® Propagati on Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Pro.
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