ODTSXN12 Data Sheet PDF | AMI





(Datasheet) ODTSXN12 PDF Download

Part Number ODTSXN12
Description CMOS Gate Array
Manufacture AMI
Total Page 2 Pages
PDF Download Download ODTSXN12 Datasheet PDF

Features: 2'76;1[[ ® $0,+*  PLFURQ &026 *DW H $UUD Description ODTSXNxx is a famil y of 4 to 24 mA, non-inverting, TTL-lev el, output buffer pieces with N-channel open-drains (pulldown) and controlled slew rate outputs. Logic Symbol Truth Table ODTSXNxx A PADM A PADM LL HZ Z = High Impedance Pad Logic HDL Synta x Verilog .................... ODTSXNxx inst_name (PADM, A); VHDL............. ......... inst_name: ODTSXNxx port map (PADM, A); Pin Loading Pin Name A (eq- load) PADM (pF) ODTSXN04 8.1 4.90 ODT SXN08 8.1 4.90 Load ODTSXN12 8.1 4.90 ODTSXN16 8.1 4.90 ODTSXN24 8.1 4.90 Power Characteristics Cell Output Driv e (mA) ODTSXN04 4 ODTSXN08 8 ODTSX N12 12 ODTSXN16 16 ODTSXN24 24 a. See page 2-15 for power equation. Pow er Characteristicsa Static IDD (TJ = 8 5°C) (nA) TBD EQLpd (Eq-load) 164.3 TBD 172.6 TBD 180.2 TBD 188.3 TBD 200.2 Propagation Delays (ns) Condi tions: TJ = 25°C, VDD = 5.0V, Typical Process Capacitive Load (pF) 15 ODTSXN04 From: A To: PADM .

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ODTSXN12 datasheet
2'76;1[[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
ODTSXNxx is a family of 4 to 24 mA, non-inverting, TTL-level, output buffer pieces with N-channel open-drains (pull-
down) and controlled slew rate outputs.
Logic Symbol
Truth Table
ODTSXNxx
A
PADM
A PADM
LL
HZ
Z = High Impedance
HDL Syntax
Verilog .................... ODTSXNxx inst_name (PADM, A);
VHDL...................... inst_name: ODTSXNxx port map (PADM, A);
Pin Loading
Pin Name
A (eq-load)
PADM (pF)
ODTSXN04
8.1
4.90
ODTSXN08
8.1
4.90
Load
ODTSXN12
8.1
4.90
ODTSXN16
8.1
4.90
ODTSXN24
8.1
4.90
Power Characteristics
Cell Output Drive (mA)
ODTSXN04
4
ODTSXN08
8
ODTSXN12
12
ODTSXN16
16
ODTSXN24
24
a. See page 2-15 for power equation.
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
164.3
TBD
172.6
TBD
180.2
TBD
188.3
TBD
200.2
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Capacitive Load (pF)
15
ODTSXN04
From: A
To: PADM
tZL
3.28
50
8.54
100
15.91
200
30.44
300 (max)
44.81
4-40

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