TELETEXT DECODER. STV5345 Datasheet

STV5345 DECODER. Datasheet pdf. Equivalent

Part STV5345
Description TELETEXT DECODER
Feature STV5345 STV5345/H - STV5345/T TELETEXT DECODER WITH 8 INTEGRATED PAGES . COMPLETE TELETEXT DECODER.
Manufacture STMicroelectronics
Datasheet
Download STV5345 Datasheet

STV5345 STV5345/H - STV5345/T TELETEXT DECODER WITH 8 INTEG STV5345 Datasheet
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STV5345
STV5345
STV5345/H - STV5345/T
TELETEXT DECODER WITH 8 INTEGRATED PAGES
. COMPLETE TELETEXT DECODER INCLUD-
. ING ON-CHIP 8 PAGES MEMORY, REDUC-
ING EMC RADIATIONS
UPWARD SOFTWARE AND HARDWARE
. COMPATIBLE WITH PREVIOUS SGS-THOM-
SON’s DECODER SDA5243
DIRECT INTERFACE TO AN EXTERNAL
STATIC RAM OF 8kBYTES FOR UP TO 16
PAGES APPLICATION
. AUTOMATIC SELECTION OF UP TO SIX NA-
TIONAL LANGUAGES
. FOUR SIMULTANEOUS PAGE REQUESTS
. DISPLAY OF THE 25TH STATUS ROW
. MICROPROCESSOR CONTROL VIA AN I2C
BUS (SLAVE ADDRESS 0010001 R/W)
. DATA ACQUISITION AVAILABLE FROM
LINES 2 TO 22 OR FROM A COMPLETE
FIELD
. HIGH QUALITY DISPLAY USING A CHARAC-
TER MATRIX OF 12 x 10 DOTS
. SINGLE + 5V SUPPLY VOLTAGE
. ON-CHIP MASK PROGRAMMABLE ROM
CHARACTER GENERATORS
. HCMOS PROCESS
DIP40
(Plastic Package)
ORDER CODE : STV5345 West European
STV5345/H East European
STV5345/T Turkish & European
PIN CONNECTIONS
VD D
A11
1
2
A12 3
OE 4
WE 5
40 A10
39 A9
38 A8
37 A7
36 A6
TTD
6
35 A5
DESCRIPTION
The STV5345 is a HCMOS integrated circuit which
performs all the processing of logical data within a
625 lines system teletext decoder. It is designed to
operate in conjunction with one-chip : the SAA5231
integrated chip which extracts Teletext information
embedded in a composite video signal. Up to 8
pages of display data can be stored in internal
memory. Using 8Kbytes of external memory leads
to a 16 pages application. A complete system also
comprises a microprocessor controlling the
STV5345 via a 2-wires serial bus. An on-chip ROM
memory contains the character sets. The STV5345
performs automatic selection of one of up to six
natural languages. Data bytes may be decoded in
either 7-Bit plus parity or in full 8-Bit formats. The
chip set also supports facilities for reception and
display of higher-level protocol data.
TTC
ODD/EVEN
F6
VCS
SAN D
TCS/SCS
R
G
B
COR
B LA N
Y
SCL
SDA
7
8
9
10
11
12
13
14
15
16
17
18
19
20
34 A4
33 A3
32 A2
31 A1
30 A0
29 D7
28 D6
27 D5
26 D4
25 D3
24 D2
23 D1
22 D0
21 VSS
April 1994
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STV5345
STV5345 - STV5345/H - STV5345/T
PIN DESCRIPTION
Pin
1
2,3,40 *
4*
5*
6
7
8
9
10
11
12
13,14,15
16
17
18
19
20
21
22-29 *
30-39 *
Symbol
VDD
A11, A12, A10
OE
WE
TTD
TTC
ODD/EVEN
F6
VCS
SAND
TCS/SCS
RGB
COR
BLAN
Y
SCL
SDA
VSS
D0-D7
A0-A9
Function
+5V
Chapter address
Output enable
Write enable
Teletext data input
Teletext clock input
Interlaced mode state output
Character display clock signal
Video composite
synchronization input signal
Sandcastle
Input / output composite
synchronization signal
Red, green, blue
Contrast reduction
Blanking signal output
Foreground output
Serial clock
Serial data input / output
0 Volt
Parallel data input / output
Address signals
Description
Positive supply voltage
Address selection outputs for 1 of 8 external static
RAM chapters each of 1 kBytes.
Active-low external static RAM output enable control
signal.
Active-low external static RAM write enable control
signal. It supports write-cycles interleaved with
read-cycles.
An A.C. coupled teletext data input supplied by the
SAA5231 chip is latched to VSS between 4 and 8µs
after each TV line.
A 6.9375MHz clock signal, supplied by the SAA5231
chip, is internally A.C. coupled, clamped and
buffered.
High for even numbered and low for odd-numbered
frames. The value is valid 2µs before the end of
lines 311 and 624.
The 6MHz clock signal, supplied by the SAA5231
chip is internally A.C. coupled, clamped and buffered.
Active high VCS input.
Three level output pulse to the SAA5231 device.
Phase lock, blanking signal, and color burst
components are contained in this signal.
Scan composite input signal (SCS) for the display
synchronization or Text composite sync. (TCS)
output signal to the SAA5231. Both signals are
active low.
Character and background colors active-high
open-drain outputs.
Open-drain active-low output supporting optimal
display of characters in ”mixed mode” operation.
Open-drain active high output for TV-image blanking
in normal and mixed-mode operation.
Open-drain active-high output with foreground
information. Can be used for printer command.
Microprocessor clock input via serial bus.
Open-drain microprocessor serial data input/output
via serial bus.
Ground.
Eight tri-state input/output for data read/write from/to
an external static RAM.
Ten addresses output pins for accessing to
individual Bytes of a 1 kByte chapter stored in an
external Static RAM.
* Pins only activated when 8KBytes of external memory are addressed, otherwise pins OE and WE remain high, and others remain low.
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