Density PLD. ISPLSI81080V Datasheet

ISPLSI81080V PLD. Datasheet pdf. Equivalent


Lattice Semiconductor ISPLSI81080V
ispLSI® 81080V
3.3V In-System Programmable
SuperBIG™ High Density PLD
Features
• SuperBIG HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 3.3V Power Supply
— 60,000 PLD Gates/1080 Macrocells
— 192-360 I/O Pins Supporting 3.3V/2.5V I/O
— 1440 Registers
— High-Speed Global and Big Fast Megablock (BFM)
Interconnect
— Wide 20-Macrocell Generic Logic Block (GLB) for
High Performance
— Wide Input Gating (44 Inputs per GLB) for Fast
Counters, State Machines, Address Decoders, Etc.
— PCB-Efficient Ball Grid Array (BGA) Package
Options
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 125 MHz Maximum Operating Frequency
tpd = 8.5 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture, Symmetrical
Generic Logic Blocks Connected by Hierarchical
Big Fast Megablock and Global Routing Planes
— Product Term Sharing Array Supports up to 28
Product Terms per Macrocell Output
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Embedded Tristate Bus Can Be Used as an Internal
Tristate Bus or as an Extension of an External
Tristate Bus
— Macrocell and I/O Registers Feature Multiple Control
Options, Including Set, Reset and Clock Enable
— I/O Pins Support Programmable Bus Hold, Pull-Up,
Open-Drain and Slew Rate Options
— Separate VCCIO Power Supply to Support 3.3V or
2.5V Input/Output Logic Levels
— I/O Cell Register Programmable as Input Register for
Fast Setup Time or Output Register for Fast Clock to
Output Time
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
12
I/O
Big Fast Megablock 0
12
I/O
12
I/O
Big Fast Megablock 1
12
I/O
12
I/O
Big Fast Megablock 2
12
I/O
12
I/O
Big Fast Megablock 3
12
I/O
12
I/O
Big Fast Megablock 4
Global Routing Plane
12
I/O
Big Fast Megablock 5
12
I/O
12
I/O
12
I/O
Big Fast Megablock 6
12
I/O
12
I/O
Big Fast Megablock 7
12
I/O
12
I/O
Boundary
Scan
Big Fast Megablock 8
12
I/O
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
81080v block
ispLSI 8000V Family Description
The ispLSI 8000V Family of Register-Intensive, 3.3V
SuperBIG In-System Programmable Logic Devices is
based on Big Fast Megablocks of 120 registered macro-
cells and a Global Routing Plane (GRP) structure
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
July 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
81080v_03
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ISPLSI81080V Datasheet
Recommendation ISPLSI81080V Datasheet
Part ISPLSI81080V
Description In-System Programmable High Density PLD
Feature ISPLSI81080V; ispLSI® 81080V 3.3V In-System Programmable SuperBIG™ High Density PLD Features • SuperBIG HIGH DENS.
Manufacture Lattice Semiconductor
Datasheet
Download ISPLSI81080V Datasheet




Lattice Semiconductor ISPLSI81080V
Specifications ispLSI 81080V
Functional Block Diagram
Figure 1. ispLSI 81080V Functional Block Diagram (Perspective)
Big Fast Megablock Routing Pool (BRP)
Big Fast Megablock Routing Pool (BRP)
Big Fast Megablock Routing Pool (BRP)
Big Fast Megablock Routing Pool (BRP)
Global Routing Plane (GRP) with Tristate Bus Lines
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Lattice Semiconductor ISPLSI81080V
Specifications ispLSI 81080V
ispLSI 8000V Family Description (Continued)
interconnecting the Big Fast Megablocks. Each Big Fast
Megablock contains 120 registered macrocells arranged
in six groups of 20, a group of 20 being referred to as a
Generic Logic Block, or GLB. Within the Big Fast
Megablock, a Big Fast Megablock Routing Pool (BRP)
interconnects the six GLBs to each other and to 24 Big
Fast Megablock I/O cells with optional I/O registers. The
Global Routing Plane which interconnects the Big Fast
Megablocks has additional global I/Os with optional I/O
registers. The 192-I/O version contains 72 Big Fast
Megablock I/Os and 120 global I/Os, while the 360-I/O
version contains 216 Big Fast Megablock I/Os and 144
global I/Os.
Outputs from the GLBs in a Big Fast Megablock can drive
both the Big Fast Megablock Routing Pool within the Big
Fast Megablock and the Global Routing Plane between
the Big Fast Megablocks. Switching resources are pro-
vided to allow signals in the Global Routing Plane to drive
any or all the Big Fast Megablocks in the device. This
mechanism allows fast, efficient connections, both within
the Big Fast Megablocks and between them.
Each GLB contains 20 macrocells and a fully populated,
programmable AND-array with 82 logic product terms.
The GLB has 44 inputs from the Big Fast Megablock
Routing Pool which are available in both true and comple-
ment form for every product term. Up to 20 of these inputs
can be switched to provide local feedback into the GLB
for logic functions that require it. The 80 general-purpose
product terms can be grouped into 20 sets of four and
sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 28 product terms for
a single function. Alternatively, the PTSA can be by-
passed for functions of four product terms or less.
The 20 registered macrocells in the GLB are driven by the
20 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a pro-
grammable register/latch/toggle flip-flop and the
necessary clocks and control logic to allow combinatorial
or registered operation. Each macrocell has two outputs,
one output can be fed back inside the GLB to the AND-
array, while the other output drives both the Big Fast
Megablock Routing Pool and the Global Routing Plane.
This dual output capability from the macrocell allows
efficient use of the hardware resources. One output can
be a registered function for example, while the other
output can be an unrelated combinatorial function.
Macrocell registers can be clocked from one of several
global, local or product term clocks available on the
device. A global, local and product term clock enable is
also provided, eliminating the need to gate the clock to
the macrocell registers. Reset and preset for the macro-
cell register is provided from both global and product term
signals. The polarity of all of these control signals is
selectable on an individual macrocell basis. The macro-
cell register can be programmed to operate as a D-type
register, a D-type flow-through latch or a T-type flip flop.
The 20 outputs from the GLB can drive both the Big Fast
Megablock Routing Pool within the Big Fast Megablock
and the Global Routing Plane between the Big Fast
Megablocks. The Big Fast Megablock Routing Pool con-
tains general purpose tracks which interconnect the six
GLBs within the Big Fast Megablock and dedicated
tracks for the signals from the Big Fast Megablock I/O
cells. The Global Routing Plane contains general pur-
pose tracks that interconnect the Big Fast Megablocks
and also carry the signals from the I/Os connected to the
Global Routing Plane.
Control signals for the I/O cell registers are generated
using an extra product term within each GLB, or using
dedicated input pins. Each GLB has two extra product
terms beyond the 80 available for the macrocell logic.
The first additional product term is used as an optional
shared product term clock for all the macrocells within the
GLB. The second additional product term is then routed
to an I/O Control Bus using a separate routing structure
from the Big Fast Megablock Routing Pool and Global
Routing Plane. Use of a separate control bus routing
structure allows the I/O registers to have many control
signals with no impact on the interconnection of the GLBs
and Big Fast Megablocks. The I/O Control Bus is split into
four quadrants, each servicing the I/O cell control re-
quirements for one edge of the device. Signals in the
control bus can be independently selected by any or all
I/O cells to act as clock, clock enable, output enable,
reset or preset.
Each Big Fast Megablock has 24 I/O cells. The Global
Routing Pool has 144 I/O cells. Each I/O cell can be
configured as a combinatorial input, combinatorial out-
put, registered input, registered output or bidirectional
I/O. I/O cell registers can be clocked from one of several
global, local or product term clocks which are selected
from the I/O control bus. A global and product term clock
enable is also provided, eliminating the need for the user
to gate the clock to the I/O cell registers. Reset and preset
for the I/O cell register is provided from both global and
product term signals. The polarity of all of these control
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