Single-Chip Driver. ILI9881C Datasheet

ILI9881C Driver. Datasheet pdf. Equivalent


ILITEK ILI9881C
ILI9881C
Amorphous TFT LCD Single-Chip Driver
800(RGB) x 1280 Resolution, 16.7M-color
Without Internal GRAM
Specification
ILI TECHNOLOGY CORP.
8F, No. 38, Taiyuan St, Jhubei City,
Taiwan 302, R.O.C.
Tel.886-3-5600099; Fax.886-3-5600585
http://www.ilitek.com
Version: V092
Document No: ILI9881C_IDT_V092_20141105


ILI9881C Datasheet
Recommendation ILI9881C Datasheet
Part ILI9881C
Description Amorphous TFT LCD Single-Chip Driver
Feature ILI9881C; ILI9881C Amorphous TFT LCD Single-Chip Driver 800(RGB) x 1280 Resolution, 16.7M-color Without Intern.
Manufacture ILITEK
Datasheet
Download ILI9881C Datasheet




ILITEK ILI9881C
a-Si TFT LCD Single Chip Driver
800(RGB) x 1280 Resolution and 16.7M-color
ILI9881C
Table of Contents
1. INTRODUCTION ........................................................................................................................................................17
2. FEATURES .................................................................................................................................................................18
3. DEVICE OVERVIEW....................................................................................................................................................20
3.1. BLOCK DIAGRAM .........................................................................................................................................................20
3.2. BLOCK FUNCTION DESCRIPTION ......................................................................................................................................21
3.2.1. System Interface .................................................................................................................................................21
3.2.2. Grayscale Voltage Generating Circuit ................................................................................................................21
3.2.3. TCON...................................................................................................................................................................21
3.2.4. OSC .....................................................................................................................................................................21
3.2.5. RAM....................................................................................................................................................................21
3.2.6. Source Driver Circuit ...........................................................................................................................................21
3.2.7. Gate Controller Circuit ........................................................................................................................................21
3.2.8. DC-to-DC Power Supply Circuit ...........................................................................................................................21
3.2.9. CABC (Content Adaptive Brightness Control) .....................................................................................................21
3.3. PIN DESCRIPTIONS........................................................................................................................................................22
3.4. PIN ASSIGNMENT .........................................................................................................................................................26
3.5. BUMP ARRANGEMENT ..................................................................................................................................................27
3.6. PAD COORDINATION.....................................................................................................................................................29
4. SYSTEM INTERFACE...................................................................................................................................................37
4.1. DSI SYSTEM INTERFACE.................................................................................................................................................37
4.1.1. General Description ............................................................................................................................................37
4.1.2. Interface Level Communication ..........................................................................................................................39
4.1.2.1. General .......................................................................................................................................................................39
4.1.2.2. DSI CLK Lanes..............................................................................................................................................................40
4.1.2.2.1. Low Power Mode (LPM) ........................................................................................................................................40
4.1.2.2.2. Ultra-Low Power Mode (ULPM) ............................................................................................................................42
4.1.2.2.3. High-Speed Clock Mode (HSCM) ...........................................................................................................................43
4.1.2.3. DSI Data Lanes ............................................................................................................................................................46
4.1.2.3.1. General..................................................................................................................................................................46
4.1.2.3.2. Escape Modes........................................................................................................................................................46
4.1.2.3.2.1. Low-Power Data Transmission (LPDT) ...........................................................................................................48
4.1.2.3.2.2. Ultra-Low Power State (ULPS)........................................................................................................................49
4.1.2.3.2.3. Remote Application Reset (RAR)....................................................................................................................50
4.1.2.3.2.4. Acknowledge (ACK)........................................................................................................................................51
4.1.2.3.3. High-Speed Data Transmission (HSDT) ..................................................................................................................52
4.1.2.3.3.1. Entering High-Speed Data Transmission (TSOT of HSDT)...............................................................................52
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
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ILITEK ILI9881C
a-Si TFT LCD Single Chip Driver
800(RGB) x 1280 Resolution and 16.7M-color
ILI9881C
4.1.2.3.3.2. Leaving High-Speed Data Transmission (TEOT of HSDT) ................................................................................53
4.1.2.3.3.3. Burst of the High-Speed Data Transmission (HSDT).......................................................................................54
4.1.2.3.4. Bus Turnaround (BTA) ...........................................................................................................................................58
4.1.3. Packet Level Communication..............................................................................................................................59
4.1.3.1. Short Packet (SPa) and Long Packet (LPa) Structures .................................................................................................59
4.1.3.1.1. Bit Order of the Byte on Packets ...........................................................................................................................60
4.1.3.1.2. Byte Order of the Multiple Byte Information on Packets......................................................................................60
4.1.3.1.3. Packet Header (PH) ...............................................................................................................................................61
4.1.3.1.3.1. Data Identification (DI)...................................................................................................................................62
4.1.3.1.3.1.1. Virtual Channel (VC) ..............................................................................................................................62
4.1.3.1.3.1.2. Data Type (DT) .......................................................................................................................................63
4.1.3.1.3.2. Packet Data (PD) in a Short Packet (SPa) .......................................................................................................65
4.1.3.1.3.3. Word Count (WC) in a Long Packet (LPa) .......................................................................................................67
4.1.3.1.3.4. Error Correction Code (ECC)...........................................................................................................................68
4.1.3.1.4. Packet Data (PD) in a Long Packet (LPa) ................................................................................................................72
4.1.3.1.5. Packet Footer (PF) in a Long Packet (LPa)..............................................................................................................72
4.1.3.2. Packet Transmissions..................................................................................................................................................74
4.1.3.2.1. Packet from the MCU to the Display Module........................................................................................................74
4.1.3.2.1.1. Display Command Set (DCS) ..........................................................................................................................74
4.1.3.2.1.2. Display Command Set (DCS) Write, No Parameter (DCSWN-S) .....................................................................75
4.1.3.2.1.3. Display Command Set (DCS) Write, 1 Parameter (DCSW1-S).........................................................................76
4.1.3.2.1.4. Display Command Set (DCS) Write Long (DCSW-L)........................................................................................77
4.1.3.2.1.5. Display Command Set (DCS) Read, No Parameter (DCSRN-S)........................................................................81
4.1.3.2.1.6. Null Packet, No Data (NP-L) ...........................................................................................................................84
4.1.3.2.1.7. End of Transmission Packet (EoTP) ................................................................................................................86
4.1.3.2.2. Packet from the Display Module to the MCU........................................................................................................88
4.1.3.2.2.1. Used Packet types..........................................................................................................................................88
4.1.3.2.2.2. Acknowledge with Error Report (AwER) ........................................................................................................89
4.1.3.2.2.3. DCS Read Long Response (DCSRR-L) ..............................................................................................................91
4.1.3.2.2.4. DCS Read Short Response, 1 Byte Returned (DCSRR1-S) ...............................................................................93
4.1.3.2.2.5. DCS Read Short Response, 2 Bytes Returned (DCSRR2-S)..............................................................................94
4.1.3.3. Communication Sequences ........................................................................................................................................95
4.1.3.3.1. General..................................................................................................................................................................95
4.1.3.3.2. Sequences .............................................................................................................................................................97
4.1.3.3.2.1. DCS Write, 1 Parameter Sequence.................................................................................................................97
4.1.3.3.2.2. DCS Write, No Parameter Sequence..............................................................................................................98
4.1.3.3.2.3. DCS Write Long Sequence..............................................................................................................................99
4.1.3.3.2.4. DCS Read, No Parameter Sequence .............................................................................................................100
4.1.3.3.2.5. Null Packet, No Data Sequence....................................................................................................................102
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 3 of 320







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