STATIC RAM. M5L8156P Datasheet

M5L8156P RAM. Datasheet pdf. Equivalent


Mitsubishi M5L8156P
MITSUBISHI LSls
MSL81S6P
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER
DESCRIPTION
The M5L8156P is a 2K-bit RAM (256-word by 8-bit) fabri-
cated with the N-channel silicon-gate EO-MOS technology.
This IC has 3 I/O ports and a 14-bit counter/timer which
make it a good choice to extend the functions of an 8-bit
microcomputer. It is incased in a 40-pin plastic OIL package
and operates with a single 5V power supply.
FEATURES
• Single 5V supply voltage
• TTL compatible
• Compatible with MELPS 85 devices
• Static RAM: 256 words by 8 bits
• Programmable 8-bit I/O port 2
• Programmable 6-bit I/O port 1
• Programmable counter/timer: 14 bits
• Multiplexed address/data bus
APPLICATION
Extension of I/O ports and timer function for MELPS 85 and
MELPS 8-48 devices
FUNCTION
The M5L8156P is composed of RAM, I/O ports and counter/
timer. The RAM is a 2K-bit static RAM organized as 256
words by 8 bits. The I/O ports consist of 2 programmable 8-
bit ports and 1 programmable 6-bit port. The terminals of the
6-bit port can be programmed to function as control termin-
als for the 8-bit ports, so that the 8-bit ports can be operated
PIN CONFIGURATION (TOP VIEW)
J PC3- 1
110 PORT C ) PC, _ 2
TIMER INPUT TIMER IN - 3
RESET INPUT RESET - 4
I/O PORT C PC5 - 5
TIMER OUTPUT TIMER OUT ~ 6
SELEC~E~~~t 10/M - 7
CHIP ENABLE INPUT CE - 8
READ INPUT RD - 9
WRITE INPUl WR -10
ADE~Jl1;lSE 1~~~~ ALE - 11
ADo-12
1/0
1PORT C
I/O
PORT B
BIDIRECTIONAL
ADDRESS/DATA BUS
I/O
PORT A
(OV)vss
Outline 40P4
in a handshake mode. The counter/timer is composed of 14
bits that can be used to count down (events or time) and it
can generate square wave pulses that can be used for
counting and timing.
a
BLOCK DIAGRAM
(5V)Vcc~ - - - - - - - - - - - - - - - - -
(ov) vss ~
STATIC RAM
(256 WORDS X 8 BITS)
BIDIRECTIONAL
ADDRESS/DATA BUS
DATA BUS
BUFFER
RESET INPUT RESET 4
MEMORY SELECT INPUT 10iM 7
CHIP ENABLE INPUT CE
READ INPUT RD
WRITE INPUT
ADDRESS LATCH
ENABLE INPUT
READ/
WRITE
CONTROL
CIRCUIT
I/O
PORT A
I/O
PORT B
I/O
PORT C
• MITSUBISHI
.... ELECTRIC
4-11


M5L8156P Datasheet
Recommendation M5L8156P Datasheet
Part M5L8156P
Description 2048-BIT STATIC RAM
Feature M5L8156P; MITSUBISHI LSls MSL81S6P 2048-BIT STATIC RAM WITH I/O PORTS AND TIMER DESCRIPTION The M5L8156P is a.
Manufacture Mitsubishi
Datasheet
Download M5L8156P Datasheet




Mitsubishi M5L8156P
MITSUBISHI LSls
MSL81S6P
2048-BIT STATIC RAM WITH I/O PORTS AND TIMER
OPERATION
Data Bus Buffer
This 3-state bidirectional 8-bit buffer is used to transfer the
data while input or output instructions are being executed by
the CPU. Command and address information is also transfer-
red through the data bus buffer.
ReadlWrite Control Logic
The read/write control logic controls the transfer of data by
interpreting I/O control bus output signals (RD, WR, 10/M
and ALE) along with CPU signal (CE). RESET signal is also
used to control the transfer of data and commands.
Bidirectional Address/Data Bus (ADo-AD7)
The bidirectional address/data bus is a3-state 8-bit bus.
The 8-bit address is latched in the internal latch by the fail-
ing edge of ALE. Then if 10/M input signal is at high-level,
the address of I/O port, counter/timer, or command register
is selected. If it is at low-level, memory address is selected.
The 8-bit address data is transferred by read input (RD)
or write input (WR).
Chip Enable Input (CE)
When CE is at high-level, the address information on
address/data bus is stored in the M5L8156P
Read Input (RD)
When RD is at lOW-level the data bus buffer is active. If 10/
M input signal is at low-level, the contents of RAM are read
through the address/data bus. If 10/M input is at high-level,
the selected contents of I/O port or counter/timer are 'read
through the address/data bus.
Write Input (WR)
When XR is at low-level, the data on the addressldata bus
are written into RAM if 101M is at low-level, or if 10/M is at
high-level they are written into I/O port, counter/timer or
command register.
Address Latch Enable Input (ALE)
An address on the address/data bus along with the levels of
CE and 10/M are latched in the M5L8156P on the falling
edge of ALE.
10/Memory Input (101M)
When 10/M is at low-level, the RAM is selected, while at
high-level the I/O port, counter/timer or command register
are selected.
I/O Port A (PAo-PA1)
Port A is an 8-bit general-purpose I/O port. Input/output set-
ting is controlled by the system software.
I/O Port B (PBo-PB7)
Port B is an 8-bit general-purpose I/O port. Input/output set-
ting is controlled by the system software.
I/O Port C (PCo-PCs)
Port C is a 6-bit I/O port that can also be used to output
control signals of port A (PA) or port B (PB). The functions
of port C are controlled by the system software. When port C
is used to output control signals of ports A or B the assign-
ment of the signals to the pins is as shown in Table 1.
Table
Pin assignment of control signals of port C
Pin
PCs
PC.
PC3
PC2
PC,.
PCa
B STB
B BF
BINTR
--
A STB
A BF
AINTR
Function
(port B strobe)
(port B buffer full)
(port B interrupt)
(port A strobe)
(port A buffer full)
(port A interrupt)
Timer Input (TIMER IN)
The signal at this input terminal is used by the counter/timer
for counting events or time. (3MHz max.)
Timer Output (TIMER OUT)
A square wave signal or pulse from the counter/timer is out-
put through this pin when in the operation mode.
Command Register (8 bits)
The command register is an 8-bit latched register. The
loworder 4 bits (bits 0-3) are used for controlling and de-
termination of the mode of the ports. Bits 4 and 5 are used
as interrupt enable flags for ports A and B when port C is
used as a control port. Bits 6 and 7 are used for controlling
the counter/timer. The contents of the command register are
rewritten by output instructions (address I/O XXXXXOOO).
Details of the functions of the individual bits of the com-
mand register are shown in Table 2.
Table 2 Bit functions of the command register
Bit Symbol
a PORT A I/O FLAG
PA
Function
1: OUTPUT PORT A
0: INPUT PORT A
-_.-
1
PORT B I/O FLAG
PB
1: OUTPUT PORT B
0: INPUT PORT B
2 PC, PORT C FLAG
3 PC2
00: ALTl
11: ALT2
01: ALT3
10: ALT4
PORT A INTERRUPT
4 lEA
ENABLE FLAG
1: ENABLE INTERRUPT
0: DISABLE INTERRUPT
PORT B INTERRUPT
1: ENABLE INTERRUPT
5 IEB
- - - _00.__ 00.- _ _ _E_NA_BL_E .F_LA_G_._._00___0_: ._D_ I..S_A_BL_E. _INT_ER_RU_PT_ _
COUNTER/TIMER CONTROL
6 TMl
00: NO INFLUENCE ON COUNTER/TIMER OPERATION
01: COUNTER/TIMER OPERATION DISCONTINUED (IF
NOT ALREADY STOPPED)
10: COUNTER/TIMER OPERATION DISCONTINUED AF-
7 TM2
TER THE CURRENT COUNTER/TIMER OPERATION
IS COMPLETED
11: COUNTER/TIMER OPERATION STARTED
4-12
• MITSUBISHI
IIhI.. ELECTRIC



Mitsubishi M5L8156P
MITSUBISHI LSls
M5L8156P
204S-BIT STATIC RAM WITH I/O PORTS AND TIMER
Status Register (7 bits)
The status register is a 7-bit latched register. The loworder 5
bits (bits 0-4) are used as status flags for the liD ports. Bit
6 is as a status flag for the counter/timer. The contents of
the status register are transferred into the CPU by reading
(INPUT instruction, address liD XXXXXOOO). Details of the
functions of the individual bits of the status register are
shown in Table 3.
Table 3 Bit functions of the status register
Bit Symbol· -i- 1 - - - - ·
0 INTR A
- - ' - ' - ' 1------- ...
PORT A INTERRUPT REOUEST
-------~-----,-----~
-
1 A BF
PORT A BUFFER FULL FLAG
2
---
_IN. TE
A
3 INTR B
PORT A INTERRUPT ENABLE
PORT B INTERRUPT REQUEST
4 B BF
PORT B BUFFER FULL FLAG
r----5 INTE B
PORT B INTERRUPT ENABLE
.-
6 TIMER
COUNTER/TIMER INTERRUPT
--
7 - THIS BIT IS NOT USED
Function
.-
(SET TO 1 WHEN THE FINAL LIMIT
OF THE COUNTER/TIMER IS REACHED
AND IS RESET TO 0 WHEN THE
STATUS IS READ)
I/O Ports
Command/status registers (8 bits/7 bits)
These register~ are assigned address XXXXXOOO. When ex-
ecuting an OUTPUT instruction, the contents of the com-
mand register are rewritten. When executing an INPUT in-
struction the contents of the status register are read.
Port A Register (8 bits)
Port A Register is assigned address XXXXX001. This register
can be programmed as an input or output by setting the
appropriate bits of the command register as shown in Table
2.
Port A can be operated in basiC or strobe made and is
aSSigned liD terminal PAa-PA7.
Port B Register (8 bits)
Port B register is assigned address XXXXX01 O. As with Port
A register, this register can be programmed as an input or
output by setting the appropriate bits of the command regis-
ter as shown in Table 2. Port B can be operated in basic or
strobe mode and is assigned liD terminals PBa-PB7.
Port C Register (6 bits)
Port C register is assigned address XXXXXOll. This port is
used for controlling input/output operations of ports A and B
by selectively setting bits 2 and 3 of the command register
as shown in Table 2. Details of the functions of the various
setting of bits 2 and 3 are shown in Table 4. Port C is
assigned liD terminals PCa - PC5 and when used as port
control signals, the 3 low-order bits are assigned for port A
while the 3 high-order bits are assigned for port B.
Table 4 Functions of port C
State
Terminal
PC5
PC,
PC3
PC2
PC,
PCo
ALT 1
Input
Input
Input
Input
Input
Input
ALT 2
ALT 3
-+--=_. - - - - - - - - , - - --------- .-----_.-._------- --- ----"--._--
ALT 4
Output
Output
B STB (port B strobe)
Output
Output
B BF (port buffer full)
Output
Output
Output
A STB (port A strobe)
B INTR (port B interrupt)
A STB (port A strobe)
Output
A BF (port A buffer full)
A BF (port A buffer full)
I Output
A INTR (port A interrupt)
A INTR (port A interrupt)
• MITSUBISHI
. . . . ELECTRIC
4-13







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)