8-Bit ADC. AD7821 Datasheet

AD7821 ADC. Datasheet pdf. Equivalent

AD7821 Datasheet
Recommendation AD7821 Datasheet
Part AD7821
Description 8-Bit ADC
Feature AD7821; a FEATURES Fast Conversion Time: 660 ns Max 100 kHz Track-and-Hold Function 1 MHz Sample Rate Unipol.
Manufacture Analog Devices
Datasheet
Download AD7821 Datasheet




Analog Devices AD7821
a
FEATURES
Fast Conversion Time: 660 ns Max
100 kHz Track-and-Hold Function
1 MHz Sample Rate
Unipolar and Bipolar Input Ranges
Ratiometric Reference Inputs
No External Clock
Extended Temperature Range Operation
Skinny 20-Lead DlPs, SOIC, and 20-Terminal
Surface-Mount Packages
LC2MOS High Speed, P Compatible
8-Bit ADC with Track/Hold Function
AD7821
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7821 is a high speed, 8-bit, sampling, analog-to-digital
converter that offers improved performance over the popular
AD7820. It offers a conversion time of 660 ns (versus 1.36 µs
for the AD7820) and 100 kHz signal bandwidth (versus 6.4
kHz). The sampling instant is better defined and occurs on the
falling edge of WR or RD. The provision of a VSS pin (Pin 19)
allows the part to operate from ± 5 V supplies and to digitize
bipolar input signals. Alternatively, for unipolar inputs, the VSS pin
can be grounded and the AD7821 will operate from a single +5 V
supply, like the AD7820.
The AD7821 has a built-in track-and-hold function capable of
digitizing full-scale signals up to 100 kHz max. It also uses a
half-flash conversion technique that eliminates the need to gen-
erate a CLK signal for the ADC.
The AD7821 is designed with standard microprocessor control
signals (CS, RD, WR, RDY, INT) and latched, three-state data
outputs capable of interfacing to high speed data buses. An
overflow output (OFL) is also provided for cascading devices to
achieve higher resolution.
The AD7821 is fabricated in Linear Compatible CMOS
(LC2MOS), an advanced, mixed technology process combining
precision bipolar circuits with low power CMOS logic. The part
features a low power dissipation of 50 mW.
PRODUCT HIGHLIGHTS
1. Fast Conversion Time
The half-flash conversion technique, coupled with fabrication
on Analog Devices’ LC2MOS process, enables a very fast con-
version time. The conversion time for the WR-RD mode is
660 ns, with 700 ns for the RD mode.
2. Built-In Track-and-Hold
This allows input signals with slew rates up to 1.6 V/µs to be
converted to 8 bits without an external track-and-hold. This
corresponds to a 5 V peak-to-peak, 100 kHz sine wave signal.
3. Total Unadjusted Error
The AD7821 features an excellent total unadjusted error figure
of less than ± 1 LSB over the full operating temperature range.
4. Unipolar/Bipolar Input Ranges
The AD7821 is specified for single-supply (+5 V) operation
with a unipolar full-scale range of 0 to +5 V, and for dual-supply
(±5 V) operation with a bipolar input range of ± 2.5 V. Typical
performance characteristics are given for other input ranges.
5. Dynamic Specifications for DSP Users
In addition to the traditional ADC specifications, the
AD7821 is specified for ac parameters, including signal-to-
noise ratio, distortion, and slew rate.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002



Analog Devices AD7821
AD7821–SPECIFICATIONS VDD = +5 V ؎ 5%, GND = 0 V. Unipolar Input Range: VSS = GND, VREF(+) = 5 V,
VREF(–) = GND. Bipolar Input Range: VSS = –5 V ؎ 5%, VREF(+) = 2.5 V,
VREF(–) = –2.5 V. These test conditions apply unless otherwise stated. All specifications TMIN to TMAX unless otherwise noted. Specifications
apply for RD Mode (Pin 7 = 0 V).
Parameter
K Version1
B, T Versions Unit
Comments
UNIPOLAR INPUT RANGE
Resolution2
8 8 Bits
Total Unadjusted Error3
±1
±1
LSB max
Minimum Resolution for which
No Missing Codes are Guaranteed 8 8 Bits
BIPOLAR INPUT RANGE
Resolution2
8 8 Bits
Zero Code Error
± 1 ± 1 LSB max
Full Scale Error
± 1 ± 1 LSB max
Signal-to-Noise Ratio (SNR)3
45
45
dB min
VIN = 99.85 kHz Full-Scale Sine Wave with fSAMPLING = 500 kHz
Total Harmonic Distortion (THD)3 –50
–50
dB max
VIN = 99.85 kHz Full-Scale Sine Wave with fSAMPLING = 500 kHz
Peak Harmonic or Spurious Noise3 –50
–50
dB max
VIN = 99.85 kHz Full-Scale Sine Wave with fSAMPLING = 500 kHz
Intermodulation Distortion (IMD)3
fa (84.72 kHz) and fb (94.97 kHz) Full-Scale Sine Waves
with fSAMPLING = 500 kHz
–50
–50
dB max
Second Order Terms
–50
–50
dB max
Third Order Terms
Slew Rate, Tracking3
1.6 1.6 V/µs max
2.36 2.36 V/µs typ
REFERENCE INPUT
Input Resistance
VREF(+) Input Voltage Range
VREF(–) Input Voltage Range
ANALOG INPUT
Input Voltage Range
Input Leakage Current
Input Capacitance
1.0/4.0
VREF(–)/VDD
VSS/VREF(+)
1.0/4.0
VREF(–)/VDD
VSS/VREF(+)
kmin/kmax
V min/V max
V min/V max
VREF(–)/VREF(+)
±3
55
VREF(–)/VREF(+)
±3
55
V min/ max
µA max
pF typ
–5 V VIN +5 V
LOGIC INPUTS
CS, WR, RD
VINH
VINL
IINH (CS, RD)
IINH (WR)
IINL
Input Capacitance4
MODE
VINH
VINL
IINH
IINL
Input Capacitance4
2.4 2.4 V min
0.8 0.8 V max
1 1 µA max
3 3 µA max
–1 –1 µA max
8
8
pF max
Typically 5 pF
3.5 3.5 V min
1.5 1.5 V max
200
200
µA max
50 µA typ
–1 –1 µA max
8
8
pF max
Typically 5 pF
LOGIC OUTPUTS
DB0–DB7, OFL, INT
VOH
4.0
4.0
V min
ISOURCE = 360 µA
VOL
0.4
0.4
V max
ISINK = 1.6 mA
IOUT (DB0–DB7)
±3
±3
µA max
Floating State Leakage
Output Capacitance4 (DB0–DB7) 8
8
pF max
Typically 5 pF
RDY
VOL
0.4
0.4
V max
ISINK = 2.6 mA
IOUT
±3
±3
µA max
Floating State Leakage
Output Capacitance4
8
8
pF max
Typically 5 pF
POWER SUPPLY
IDD5
ISS
Power Dissipation
Power Supply Sensitivity
20
100
50
± 1/4
20
100
50
± 1/4
mA max
µA max
mW typ
LSB max
CS = RD = 0 V
CS = RD = 0 V
± 1/16 LSB typ, VDD = 4.75 V to 5.25 V,
(VREF(+) = 4.75 V max for Unipolar Mode)
NOTES
1Temperature Ranges are as follows: K Version = –40°C to +85°C; B Version = –40°C to +85°C; T Version = –55°C to +125°C.
21 LSB = 19.53 mV for both the unipolar (0 V to +5 V) and bipolar (–2.5 V to +2.5 V) input ranges.
3See Terminology.
4Sample tested at +25°C to ensure compliance.
5See Typical Performance Characteristics.
Specifications subject to change without notice.
–2– REV. B



Analog Devices AD7821
AD7821
TIMING CHARACTERISTICS1 (VDD = +5 V ؎ 5%, VSS = 0 V or –5 V ؎ 5%; Unipolar or Bipolar Input Range)
Parameter
Limit at +25؇C
(All Versions)
Limit at
TMIN, TMAX
(K, B Versions)
Limit at
TMIN, TMAX
(T Version)
Unit
Conditions/Comments
tCSS
tCSH
tRDY2
tCRD
tACC03
tINTH2
tDH4
tP
tWR
tRD
tREAD1
tACC13
tRI
tINTL2
tREAD2
tACC23
tIHWR2
tID3
0
0
70
700
tCRD + 25
tCRD + 50
50
80
15
60
350
250
10
250
160
160
185
150
380
500
65
65
90
80
30
45
0
0
85
875
tCRD + 30
tCRD + 65
85
15
70
425
325
10
350
205
205
235
185
610
75
75
110
100
35
60
0
0
100
975
tCRD + 35
tCRD + 75
90
15
80
500
400
10
450
240
240
275
220
700
85
85
130
120
40
70
ns min
ns min
ns max
ns max
ns max
ns max
ns typ
ns max
ns min
ns max
ns min
ns min
µs max
ns min
ns min
ns max
ns max
ns max
ns typ
ns max
ns min
ns max
ns max
ns max
ns max
ns max
CS to RD/WR Setup Time
CS to RD/WR Hold Time
CS to RDY Delay. Pull-Up
Resistor 5 k
Conversion Time (RD Mode)
Data Access Time (RD Mode)
CL = 20 pF
CL = 100 pF
RD to INT Delay (RD Mode)
Data Hold Time
Delay Time Between Conversions
Write Pulsewidth
Delay Time between WR and RD Pulses
RD Pulsewidth (WR-RD Mode, see Figure 12b)
Determined by tACC1
Data Access Time (WR-RD Mode, see Figure 12b)
CL = 20 pF
CL = 100 pF
RD to INT Delay
WR to INT Delay
RD Pulsewidth (WR-RD Mode, see Figure 12a)
Determined by tACC2
Data Access Time (WR-RD Mode, see Figure 12a)
CL = 20 pF
CL = 100 pF
WR to INT Delay (Stand-Alone Operation)
Data Access Time after INT
(Stand-Alone Operation)
CL = 20 pF
CL = 100 pF
NOTES
1Sample tested at +25°C to ensure compliance. All input control signals are specified with tRISE = tFALL = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2CL = 50 pF.
3Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
a. High Z to VOH
b. High Z to VOL
Figure 1. Load Circuits for Data Access Time Test
ORDERING GUIDE
Model1
Temperature
Range
Total
Unadjusted Package
Error (LSB) Option2
AD7821KN
AD7821KP
AD7821KR
AD7821BQ
AD7821TQ
AD7821TE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
± 1 max
± 1 max
± 1 max
± 1 max
± 1 max
± 1 max
N-20
P-20A
RW-20
Q-20
Q-20
E-20A
NOTES
1To order MIL-STD-883, Class B processed parts, add /883B to part
number. Contact local sales office for military data sheet.
2E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded
Chip Carrier; Q = Cerdip; R = SOIC.
a. VOH to High Z
b. VOL to High Z
Figure 2. Load Circuits for Data Hold Time Test
REV. B
–3–







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