The efficiency of a switching regulator is equal to the output power divided by the input power times
100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which
change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (L1+
L2+ L3+ ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all
dissipative elements in the circuit produce losses, two main sources usually account for most of the
losses: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency
loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading
since the actual power lost is of no consequence.
1. The VIN quiescent current is due to two components: the DC bias current as given in the electrical
characteristics and the internal main switch and synchronous switch gate charge currents. The gate
charge current results from switching the gate capacitance of the internal power MOSFET switches.
Each time the gate is switched from high to low to high again, a packet of charge ΔQ moves from VIN to
ground. The resulting ΔQ/Δt is the current out of VIN that is typically larger than the DC bias current. In
continuous mode, IGATECHG = f (QT+QB) where QT and QB are the gate charges of the internal top and
bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects
will be more pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the internal switches, RSW and external inductor RL.
In continuous mode the average output current flowing through inductor L is “chopped” between the
main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a
function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = RDS(ON)TOP x
DC + RDS(ON)BOT x (1-DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the
Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and
multiply the result by the square of the average output current. Other losses including CIN and COUT ESR
dissipative losses and inductor core losses generally account for less than 2% of the total loss.
Board Layout Suggestions
When laying out the printed circuit board, the following checklist should be used to ensure proper
operation of the HX1304G. Check the following in your layout.
1. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept
short, direct and wide.
2. Put the input capacitor as close as possible to the device pins (VIN and GND).
3. SW node is with high frequency voltage swing and should be kept small area. Keep analog
components away from SW node to prevent stray capacitive noise pick-up.
4. Connect all analog grounds to a command node and then connect the command node to the power
ground behind the output capacitors.