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Audio ADC. ES7210 Datasheet

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Audio ADC. ES7210 Datasheet
















ES7210 ADC. Datasheet pdf. Equivalent













Part

ES7210

Description

High Performance Four Channels Audio ADC



Feature


ES7210 High Performance Four Channels Au dio ADC FEATURES • High performance multi-bit delta-sigma audio ADC • 102 dB signal to noise ratio • -85 dB TH D+N • 24-bit, 8 to 200 kHz sampling f requency • I2S/PCM master or slave se rial data port • Support TDM • 256/ 384Fs, USB 12/24 MHz and other non stan dard audio system clocks • Low power standby mode APPLICATIONS • Mic a.
Manufacture

Everest Semiconductor

Datasheet
Download ES7210 Datasheet


Everest Semiconductor ES7210

ES7210; rray • Smart speaker • Far field voi ce capture ORDERING INFORMATION ES7210 -40°C ~ +85°C QFN-32 BLOCK DIAGRAM MIC1P/MIC1N MIC2P/MIC2N MIC3P/MIC3N MIC 4P/MIC4N Multi-bit Delta-sigma Modulat or DSP Clock Manager Sample Rate Dete ctor MCLK SDOUT2/TDMIN Audio Data Int erface SDOUT1/TDMOUT SCLK LRCK I2C In terface CCLK CDATA AD0 AD1 1 Everest Semiconductor Confident.


Everest Semiconductor ES7210

ial 1. PIN OUT AND DESCRIPTION ES7210 REFQM MICBIAS34 MIC4N MIC4P REFP34 REF Q34 MIC3P MIC3N 25 26 27 28 29 30 31 3 2 AD0 AD1 CDATA CCLK MCLK VDDP VDDD GN DD 1 2 3 4 5 6 7 8 ES7210 24 MICBIAS 12 23 VDDM 22 VDDA 21 GNDA 20 MIC2N 19 M .


Everest Semiconductor ES7210

.





Part

ES7210

Description

High Performance Four Channels Audio ADC



Feature


ES7210 High Performance Four Channels Au dio ADC FEATURES • High performance multi-bit delta-sigma audio ADC • 102 dB signal to noise ratio • -85 dB TH D+N • 24-bit, 8 to 200 kHz sampling f requency • I2S/PCM master or slave se rial data port • Support TDM • 256/ 384Fs, USB 12/24 MHz and other non stan dard audio system clocks • Low power standby mode APPLICATIONS • Mic a.
Manufacture

Everest Semiconductor

Datasheet
Download ES7210 Datasheet




 ES7210
ES7210
High Performance Four Channels Audio ADC
FEATURES
High performance multi-bit delta-sigma
audio ADC
102 dB signal to noise ratio
-85 dB THD+N
24-bit, 8 to 200 kHz sampling frequency
I2S/PCM master or slave serial data port
Support TDM
256/384Fs, USB 12/24 MHz and other
non standard audio system clocks
Low power standby mode
APPLICATIONS
Mic array
Smart speaker
Far field voice capture
ORDERING INFORMATION
ES7210 -40°C ~ +85°C
QFN-32
BLOCK DIAGRAM
MIC1P/MIC1N
MIC2P/MIC2N
MIC3P/MIC3N
MIC4P/MIC4N
Multi-bit
Delta-sigma
Modulator
DSP
Clock Manager
Sample Rate Detector
MCLK
SDOUT2/TDMIN
Audio
Data
Interface
SDOUT1/TDMOUT
SCLK
LRCK
I2C
Interface
CCLK CDATA AD0 AD1
1




 ES7210
Everest Semiconductor
Confidential
1. PIN OUT AND DESCRIPTION
ES7210
AD0
AD1
CDATA
CCLK
MCLK
VDDP
VDDD
GNDD
1
2
3
4
5
6
7
8
ES7210
24 MICBIAS12
23 VDDM
22 VDDA
21 GNDA
20 MIC2N
19 MIC2P
18 REFQ12
17 REFP12
Pin Name
CCLK, CDATA
AD0, AD1
MCLK
SCLK
LRCK
SDOUT1/TDMOUT
SDOUT2/TDMIN
INT
DMIC_CLK
MIC1P, MIC1N
MIC2P, MIC2N
MIC3P, MIC3N
MIC4P, MIC4N
MICBIAS12
MICBIAS34
VDDP
VDDD, GNDD
VDDA, GNDA
VDDM
REFP12, REFP34
REFQ12, REFQ34
REFQM
Pin number
3, 4
1, 2
5
9
10
11
12
13
14
16, 15
19, 20
31, 32
28, 27
24
26
6
7, 8
22, 21
23
17, 29
18, 30
25
Input or Output
I/O
I
I
I/O
I/O
O
I/O
O
O
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Pin Description
I2C clock and data
I2C address
Master clock
Serial data bit clock
Serial data left and right channel frame clock
Serial data output or TDM data input and output
Interrupt
Digital mic clock
Mic input
Mic bias
Power supply for the digital input and output
Digital power supply
Analog power supply
Analog power supply
Filtering capacitor connection
Filtering capacitor connection
Filtering capacitor connection
Revision 3.0
2
May 2018




 ES7210
Everest Semiconductor
Confidential
ES7210
2. TYPICAL APPLICATION CIRCUIT
VDDP
VDDC
IIC
IIS
GPIO
1uF 100nF
6
7
1uF 100n8F
1
2
3
4
100K
5
9
10
11
12
V1D3DP
14
AGND
VDDM
1R
10uF 10uF 10uF 10uF 10uF
10uF
AGND
100nF
1R
VDDA
VDDP
VDDD
GNDD
AD0
AD1
CDATA
CCLK
MCLK
SCLK
LRCK
SDOUT1/TDMOUT
SDOUT2/TDMIN
INT
ES7210
Everest
DMIC_CLK
10uF 100nF
AGND
AGND
10uF 100nF
AGND
MICBIAS34
MIC4P
MIC4N
MIC3P
MIC3N
26
28
27
31
32
AGND
10uF
10nF 10nF 10nF 10nF2K
2.2uF
2.2uF
2.2uF
2.2uF
100nF
AGND
MICBIAS12
MIC2P
MIC2N
MIC1P
MIC1N
24
19
20
16
15
10nF 10nF 10nF 10nF2K
2.2uF
2.2uF
2.2uF
2.2uF
For best performance,decoupling and filter capacitor should be located as close to the device package as possible
AGND AGND
2K 2K 2K
Mic4
Mic3
AGND AGND
2K 2K 2K
Mic2
Mic1
3. CLOCK MODES AND SAMPLING FREQUENCIES
The device supports standard audio clocks (256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz),
and some common non standard audio clocks (25 MHz, 26 MHz, etc).
According to the serial audio data sampling frequency (Fs), the device can work in two speed
modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges
from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz.
The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and
SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the
system clock with specific rates. In master mode, LRCK and SCLK are derived internally from
device master clock.
4. MICRO-CONTROLLER CONFIGURATION INTERFACE
The device supports standard I2C micro-controller configuration interface. External micro-
controller can completely configure the device through writing to internal configuration
registers.
I2C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock
line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in
Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on
a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being
transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull
the CDATA low. The transfer rate of this interface can be up to 400 kbps.
Revision 3.0
3
May 2018




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