Buck Regulator. MIC26603-ZA Datasheet
28V, 6A Hyper Speed Control
Synchronous DC-to-DC Buck Regulator
The Micrel MIC26603-ZA is a constant-frequency,
synchronous buck regulator featuring a unique adaptive
ON-time control architecture. The MIC26603-ZA operates
over an input supply range of 4.5V to 28V and provides a
regulated output of up to 6A of output current. The output
voltage is adjustable down to 0.6V with a guaranteed
accuracy of ±1%, and the device operates at a switching
frequency of 600kHz.
Micrel’s Hyper Speed Control architecture allows for
ultra-fast transient response while reducing the output
capacitance and also makes (High VIN)/(Low VOUT)
operation possible. This adaptive tON ripple control
architecture combines the advantages of fixed-frequency
operation and fast transient response in a single device.
The MIC26603-ZA offers a full suite of features to ensure
protection of the IC during fault conditions. These include
undervoltage lockout to ensure proper operation under
power-sag conditions, internal soft-start to reduce inrush
current, foldback current limit, “hiccup mode” short-circuit
protection, and thermal shutdown. An open-drain Power
Good (PG) pin is provided.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
• Hyper Speed Control architecture enables
− High Delta V operation (VIN = 28V and VOUT = 0.6V)
− Small output capacitance
• 4.5V to 28V voltage input
• 6A output current capability, up to 95% efficiency
• Adjustable output from 0.6V to 5.5V
• ±1% feedback accuracy
• Any Capacitor stable - zero-to-high ESR
• 600kHz switching frequency
• No external compensation
• Power Good (PG) output
• Foldback current limit and short-circuit protection
• Supports safe startup into a pre-biased load
• –40°C to +125°C junction temperature range
• 28-pin 5mm × 6mm QFN package
• Distributed power systems
• Communications/networking infrastructure
• Set-top box, gateways, and routers
• Printers, scanners, graphic cards, and video cards
Efficiency (VIN = 12V)
vs. Output Current
OUTPUT CURRENT (A)
Hyper Speed Control, SuperSwitcher, and Any Capacitor are trademarks of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
July 16, 2014
28-Pin 5mm × 6mm QFN
–40°C to +125°C
28-Pin 5mm × 6mm QFN (JL)
2, 5, 6, 7,
4, 9, 10,
5V Internal Linear Regulator output: PVDD supply is the power MOSFET gate drive supply voltage
created by internal LDO from VIN. When VIN < +5.5V, PVDD should be tied to the PVIN pins. A 2.2µF
ceramic capacitor from the PVDD pin to PGND (pin 2) must be placed next to the IC.
Power Ground: PGND is the ground path for the buck converter power stage. The PGND pins connect
to the low-side N-Channel internal MOSFET gate drive supply ground, the sources of the MOSFETs,
the negative terminals of input capacitors, and the negative terminals of output capacitors. The loop
for the power ground should be as small as possible and separate from the signal ground (SGND)
Switch Node output: Internal connection for the high-side MOSFET source and low-side MOSFET
drain. Because of the high-speed switching on this pin, the SW pin should be routed away from
High-Side N-internal MOSFET Drain Connection input: The PVIN operating voltage range is from 4.5V
to 28V. Input capacitors between the PVIN pins and the power ground (PGND) are required and keep
the connection short.
Boost output: Bootstrapped voltage to the high-side N-channel MOSFET driver. A Schottky diode is
connected between the PVDD pin and the BST pin. A boost capacitor of 0.1μF is connected between
the BST pin and the SW pin. Adding a small resistor at the BST pin can reduce the turn-on time of
high-side N-Channel MOSFETs.
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Pin Description (Continued)
Current Sense input: The CS pin senses current by monitoring the voltage across the low-side
MOSFET during the OFF-time. The current sensing is necessary for short circuit protection. To sense
the current accurately, connect the low-side MOSFET drain to SW using a Kelvin connection. The CS
pin is also the high-side MOSFET’s output driver return.
Signal Ground: SGND must be connected directly to the ground planes. Do not route the SGND pin to
the PGND pad on the top layer (see “PCB Layout Guidelines” for details).
Feedback input: Input to the transconductance amplifier of the control loop. The FB pin is regulated to
0.6V. A resistor divider connecting the feedback to the output is used to adjust the desired output
Power Good output: Open drain output. The PG pin is externally tied with a resistor to VDD. A high
output is asserted when VOUT > 92% of nominal.
Enable input: A logic level control of the output. The EN pin is CMOS-compatible. Logic high = enable,
logic low = shutdown. In the off state, the supply current of the device is greatly reduced (typically
5µA). Do not leave the EN pin floating.
Power Supply Voltage input: Requires a bypass capacitor to SGND.
5V Internal Linear Regulator output: VDD supply is the power MOSFET gate drive supply voltage and
the supply bus for the IC. VDD is created by internal LDO from VIN. When VIN < +5.5V, VDD should
be tied to PVIN pins. A 1µF ceramic capacitor from the VDD pin to SGND pins must be placed next to
July 16, 2014