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LVPECL-CMOS Oscillator. DSC2021 Datasheet

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LVPECL-CMOS Oscillator. DSC2021 Datasheet






DSC2021 Oscillator. Datasheet pdf. Equivalent




DSC2021 Oscillator. Datasheet pdf. Equivalent





Part

DSC2021

Description

Low-Jitter Configurable Dual LVPECL-CMOS Oscillator



Feature


DSC2021 Low-Jitter Configurable Dual LV PECL-CMOS Oscillator General Descripti on The DSC2021 series of high performa nce dual output oscillators utilize a proven silicon MEMS technology to prov ide excellent jitter and stability whi le incorporating additional device fun ctionality. The two outputs are contro lled by separate supply voltages to al low for independen.
Manufacture

Discera

Datasheet
Download DSC2021 Datasheet


Discera DSC2021

DSC2021; t voltage level control. The frequencie s of the outputs can be identical or i ndependently derived from a common PLL frequency source. The DSC2021 has pr ovision for up to eight user- defined pre-programmed, pin-selectable output frequency combinations. The DSC2021 i s also equipped with independent pin-s electable output drive strengths for th e CMOS output to .


Discera DSC2021

reduce EMI and noise. DSC2021 is packag ed in a 14-pin 3.2x2.5 mm QFN package a nd available in temperature grades from Ext. Commercial to Industrial. Block Diagram Features Low RMS Phase Jitter: <1 ps (typ) High Stability: ±10, ±25 , ±50 ppm Wide Temperatu .


Discera DSC2021

.

Part

DSC2021

Description

Low-Jitter Configurable Dual LVPECL-CMOS Oscillator



Feature


DSC2021 Low-Jitter Configurable Dual LV PECL-CMOS Oscillator General Descripti on The DSC2021 series of high performa nce dual output oscillators utilize a proven silicon MEMS technology to prov ide excellent jitter and stability whi le incorporating additional device fun ctionality. The two outputs are contro lled by separate supply voltages to al low for independen.
Manufacture

Discera

Datasheet
Download DSC2021 Datasheet




 DSC2021
DSC2021
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
General Description
The DSC2021 series of high performance
dual output oscillators utilize a proven silicon
MEMS technology to provide excellent jitter
and stability while incorporating additional
device functionality. The two outputs are
controlled by separate supply voltages to
allow for independent voltage level control.
The frequencies of the outputs can be
identical or independently derived from a
common PLL frequency source.
The
DSC2021 has provision for up to eight user-
defined pre-programmed, pin-selectable
output frequency combinations.
The
DSC2021 is also equipped with independent
pin-selectable output drive strengths for the
CMOS output to reduce EMI and noise.
DSC2021 is packaged in a 14-pin 3.2x2.5
mm QFN package and available in
temperature grades from Ext. Commercial to
Industrial.
Block Diagram
Features
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o Industrial: -40° to 85° C
o Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
Two Independent Outputs
o LVPECL and CMOS
Pin-Selectable Configurations
o 3-bit Output Drive Strength (CMOS)
o 3-bit Output Frequency Combinations
Short Lead Times: 2 Weeks
Wide Frequency Range
o LVPECL Output: 2.3 to 460 MHz
o CMOS Output: 2.3 to 170 MHz
Miniature Footprint of 3.2x2.5mm
Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
High Reliability
o 20x better MTF than quartz oscillators
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Applications
Storage Area Networks
o SATA, SAS, Fibre Channel
Passive Optical Networks
o EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express
_____________________________________________________________________________________________________________________________ _________________
DSC2021
Page 1
MK-Q-B-P-D-12042604-2




 DSC2021
DSC2021
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
Enable
NC
OS0
GND
FS0
FS1
FS2
Output1+
Output1-
OS1
Output 2
VDD2
VDD
OS2
Pin
Type
I
NA
I
Power
I
I
I
O
O
I
O
Power
Power
I
Description
Enables outputs when high and disables (tri-state) them when low
Leave unconnected or grounded
Least significant bit for output drive strength selection for CMOS
Ground
Least significant bit for frequency selection
Middle bit for frequency selection
Most significant bit for frequency selection
Positive LVPECL Output 1
Negative LVPECL Output 1
Middle bit for output drive strength selection for CMOS
CMOS output
Power Supply 2 for CMOS Output
Power Supply
Most significant bit for output drive strength selection for CMOS
Operational Description
The DSC2021 is a dual output LVPECL-CMOS
oscillator consisting of a MEMS resonator and
a support PLL IC. The two outputs, CMOS and
LVPECL, are generated through independent
8-bit programmable dividers from the output
of the internal PLL. Two constraints are
imposed on the output frequencies: 1) f2=M x
f1/N, where M and N are even integers
between 4 and 254, 2) 1.2GHz < N x f2 <
1.7GHz.
The actual frequencies output by the DSC2021
are controlled by an internal pre-programmed
memory (OTP). This memory stores all
coefficients required by the PLL for up to eight
different frequency combinations. Three
control pins (FS0 FS2) select the output
frequency combination. Discera supports
customer defined versions of the DSC2021.
Standard frequency options are described in in
the following sections.
The DSC2021 provides control of the output
voltage levels of the CMOS output. VDD2 (pin
12) sets the high voltage level of Output 2 and
must be equal to or less than VDD at all times
to insure proper operation. VDD2 can be as
low as 1.65V.
When Enable (pin 1) is floated or connected to
VDD, the DSC2021 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
The DSC2021 has programmable output drive
strength for CMOS output. Using three control
pins (OS0-OS2), the drive strength for CMOS
output (output 2) can be adjusted to match
circuit board impedances to reduce power
supply noise, overshoot/undershoot and EMI.
Table 1 displays typical rise / fall times for the
output with a 15pf load capacitance as a
function of these control pins at VDD=3.3V
and room temperature.
Table 1. Rise/Fall times for drive strengths
Output Drive Strength Bits
[OS2, OS1, OS0] - Default [111]
000 001 010 011 100 101 110 111
tr (ns) 2.1 1.7 1.6 1.4 1.3 1.3 1.2 1.1
tf (ns) 2.5 2.4 2.4 2 1.8 1.6 1.3 1.3
_____________________________________________________________________________________________________________________________ _________________
DSC2021
Page 2
MK-Q-B-P-D-12042604-2




 DSC2021
DSC2021
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
Output Clock Frequencies
Table 2 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code above. Customer defined combinations are available.
Table 2. Pre-programmed pin-selectable output frequency combinations
Ordering
Info
Freq
(MHz)
Freq Select Bits [FS2, FS1, FS0] Default is [111]
000 001 010 011 100 101 110 111
I0001
I000X
fOUT1
fOUT2
fOUT1
fOUT2
150
75
150 125 100 150 156.25 125
50 50 50 25 25 25
Contact factory for additional configurations.
100
25
Frequency select bit are weakly tied high so if left unconnected the default setting will be [111] and
the device will output the associated frequency highlighted in Bold.
Absolute Maximum Ratings
Item
Min Max Unit
Supply Voltage -0.3 +4.0
V
Input Voltage
Junction Temp
-0.3 VDD+0.3
- +150
V
°C
Storage Temp -55 +150
°C
Soldering Temp -
+260
°C
ESD
-
HBM
4000
MM 400
CDM
1500
Note: 1000+ years of data retention on internal memory
V
Condition
40sec max.
Ordering Code
Temp Range
E: -20 to 70
I: -40 to 85
Packing
T: Tape & Reel
: Tube
DSC2021 F I 2 - xxxxx
T
Package
F: 3.2x2.5mm
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Freq (MHz)
See Freq. table
_____________________________________________________________________________________________________________________________ _________________
DSC2021
Page 3
MK-Q-B-P-D-12042604-2



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