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Fanout Buffer. PL135-37 Datasheet

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Fanout Buffer. PL135-37 Datasheet






PL135-37 Buffer. Datasheet pdf. Equivalent




PL135-37 Buffer. Datasheet pdf. Equivalent





Part

PL135-37

Description

1:3 Oscillator Fanout Buffer



Feature


PL135-37 Low Power, 1.62V to 3.63V, 10M Hz to 40MHz, 1:3 Oscillator Fanout Buff er FE AT UR E S Advanced Oscillator D esign for Wide Frequency Coverage 3 LV CMOS Outputs 12 mA Output Drive Streng th Input/Output Frequency: o Fundament al Crystal: 10MHz to 40MHz Very Low Ji tter and Phase Noise Low Current Consu mption Single 1.62V to 3.63V Power Sup ply Available in .
Manufacture

Micrel

Datasheet
Download PL135-37 Datasheet


Micrel PL135-37

PL135-37; SOP-8L GREEN/RoHS Compliant Package DES CRIPTION The PL135-37 is an advanced os cillator fanout buffer design for high performance, low-power applications. Th e PL135-37 accepts a fundamental crysta l input of 10MHz to 40MHz and produces three LVCMOS outputs of the same freque ncy. The Output Enable (OE) function ca n be used to tri-state the outputs. The PL135-27 offers t.


Micrel PL135-37

he best phase noise and jitter performan ce and lowest power consumption of any comparable IC. PACKAGE PIN CONFIGURATI ON XIN OE^ CLK1 GND 18 27 36 45 SOP-8L XOUT CLK0 VDD CLK2 BLOCK DIAGRAM XI N XOUT OE XTAL OSC CLK0 CLK1 CLK2 Mi c .


Micrel PL135-37

.

Part

PL135-37

Description

1:3 Oscillator Fanout Buffer



Feature


PL135-37 Low Power, 1.62V to 3.63V, 10M Hz to 40MHz, 1:3 Oscillator Fanout Buff er FE AT UR E S Advanced Oscillator D esign for Wide Frequency Coverage 3 LV CMOS Outputs 12 mA Output Drive Streng th Input/Output Frequency: o Fundament al Crystal: 10MHz to 40MHz Very Low Ji tter and Phase Noise Low Current Consu mption Single 1.62V to 3.63V Power Sup ply Available in .
Manufacture

Micrel

Datasheet
Download PL135-37 Datasheet




 PL135-37
PL135-37
Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:3 Oscillator Fanout Buffer
FE AT UR E S
Advanced Oscillator Design for Wide
Frequency Coverage
3 LVCMOS Outputs
12 mA Output Drive Strength
Input/Output Frequency:
o Fundamental Crystal: 10MHz to 40MHz
Very Low Jitter and Phase Noise
Low Current Consumption
Single 1.62V to 3.63V Power Supply
Available in SOP-8L GREEN/RoHS Compliant
Package
DESCRIPTION
The PL135-37 is an advanced oscillator fanout buffer
design for high performance, low-power applications.
The PL135-37 accepts a fundamental crystal input of
10MHz to 40MHz and produces three LVCMOS out-
puts of the same frequency. The Output Enable
(OE) function can be used to tri-state the outputs.
The PL135-27 offers the best phase noise and jitter
performance and lowest power consumption of any
comparable IC.
PACKAGE PIN CONFIGURATION
XIN
OE^
CLK1
GND
18
27
36
45
SOP-8L
XOUT
CLK0
VDD
CLK2
BLOCK DIAGRAM
XIN
XOUT
OE
XTAL
OSC
CLK0
CLK1
CLK2
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/18/11 Page 1




 PL135-37
PL135-37
Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:3 Oscillator Fanout Buffer
PIN DESCRIPTION
Name SOP-8L Type
Description
XIN 1 I Crystal input
OE
2
I
Output enable input. This pin has internal pull-up resistor. All outputs will be
tri-stated when pulled low.
CLK1 3 O Output clock
GND 4 P Ground connection
CLK2 5 O Output clock
VDD 6 P Power supply
CLK0 7 O Output clock
XOUT
8
I Crystal output
* Note: This pin includes an internal 60KΩ pull up.
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper ter-
mination this will cause reflections (looks like ringing).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with V DD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical value to use is 0.1F.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
(Typical buffer impedance 20Ω)
50Ω line
To CMOS Input
Crystal Tuning Circuit
Series and parallel capacitors used to fine tune the crystal load to the circuit load.
Crystal
Cst
Series Resistor
Use value to match output buffer impedance to
50Ω trace. Typical value 30Ω
XIN
1
Cpt
XOUT
8
Cpt
CST Series Capacitor, used to lower circuit load to match crystal load. Raises frequency offset.
This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator.
CPT Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers
frequency offset.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/18/11 Page 2




 PL135-37
PL135-37
Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:3 Oscillator Fanout Buffer
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
VDD -0.5
4.6 V
Input Voltage Range
VI
-0.5
VDD+0.5
V
Output Voltage Range
VO
-0.5
VDD+0.5
V
Storage Temperature
TS -65
150 C
Ambient Operating Temperature*
-40 85 C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permane nt
damage to the device and affect product reliability. These conditions repr esent a stress rating only, and functional operations of the
device at these or any other conditions above the operational limits noted in this specif ication is not implied. *Operating temperature is
guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency
Settling Time
Output Enable Time
VDD Sensitivity
Output Rise Time
Output Fall Time
Output to Output Skew
Duty Cycle
CONDITIONS
Fundamental Crystal
At power-up (VDD > 1.62V)
OE Function; Ta=25º C, 10pF Load
Frequency vs. VDD, ±10%
15pF Load, 10/90% VDD, 3.3V
15pF Load, 90/10% VDD, 3.3V
Under all conditions
Under all conditions
MIN. TYP. MAX. UNITS
10 40 MHz
5 ms
10 ns
-1 1 ppm
2 3 ns
2 3 ns
250 ps
45 50 55 %
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
Supply Current, Dynamic
Supply Current, Standby
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current
IDD
ID D_ S B
VDD
VOL
VOH
IOSD
VDD = 3.3V, 25MHz, No Load
VDD = 2.5V, 25MHz, No Load
VDD = 1.8V, 25MHz, No Load
OE Pin Pulled Low, 25MHz,
3.3V
IOL = +12mA, 3.3V
IOH = -12mA, 3.3V
VOL = 0.4V, VOH = 2.4V
MIN TYP MAX UNITS
4 mA
3 mA
2 mA
0.6 mA
1.62 3.63 V
0.4 V
2.4 V
12 mA
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/18/11 Page 3



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