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Fanout Buffer. PL135-67 Datasheet

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Fanout Buffer. PL135-67 Datasheet






PL135-67 Buffer. Datasheet pdf. Equivalent




PL135-67 Buffer. Datasheet pdf. Equivalent





Part

PL135-67

Description

1:6 Oscillator Fanout Buffer



Feature


PL135-67 Low Power, 1.62V to 3.63V, 10MH z to 40MHz, 1:6 Oscillator Fanout Buffe r FE AT UR E S Advanced Oscillator De sign for Wide Frequency Coverage 6 LVC MOS Outputs with 2 Output Enable Pins 8mA Output Drive Strength Input/Output Frequency: o Fundamental Crystal: 10MH z to 40MHz Very Low Jitter and Phase N oise Low Current Consumption Single 1 .62V to 3.63V Powe.
Manufacture

Micrel

Datasheet
Download PL135-67 Datasheet


Micrel PL135-67

PL135-67; r Supply Available in QFN-16L and TSSOP -16L GREEN/RoHS Compliant Packages DES CRIPTION The PL135-67 is an advanced os cillator fanout buffer design for high performance, low-power, small formfacto r applications. The PL135-67 accepts a fundamental input crystal of 10MHz to 4 0MHz and produces six outputs of the sa me frequency, two with their own Output Enable functions..


Micrel PL135-67

Offered in a small 3 x 3mm QFN or TSSOP package, the PL135-67 offers the best phase noise and jitter performance and lowest power consumption of any compara ble IC. PACKAGE PIN CONFIGURATION GND XIN XOUT VDD CLK4 CLK5 VDD OE0 1312 1 .


Micrel PL135-67

.

Part

PL135-67

Description

1:6 Oscillator Fanout Buffer



Feature


PL135-67 Low Power, 1.62V to 3.63V, 10MH z to 40MHz, 1:6 Oscillator Fanout Buffe r FE AT UR E S Advanced Oscillator De sign for Wide Frequency Coverage 6 LVC MOS Outputs with 2 Output Enable Pins 8mA Output Drive Strength Input/Output Frequency: o Fundamental Crystal: 10MH z to 40MHz Very Low Jitter and Phase N oise Low Current Consumption Single 1 .62V to 3.63V Powe.
Manufacture

Micrel

Datasheet
Download PL135-67 Datasheet




 PL135-67
PL135-67
Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:6 Oscillator Fanout Buffer
FE AT UR E S
Advanced Oscillator Design for Wide
Frequency Coverage
6 LVCMOS Outputs with 2 Output Enable Pins
8mA Output Drive Strength
Input/Output Frequency:
o Fundamental Crystal: 10MHz to 40MHz
Very Low Jitter and Phase Noise
Low Current Consumption
Single 1.62V to 3.63V Power Supply
Available in QFN-16L and TSSOP-16L
GREEN/RoHS Compliant Packages
DESCRIPTION
The PL135-67 is an advanced oscillator fanout buffer
design for high performance, low-power, small form-
factor applications. The PL135-67 accepts a
fundamental input crystal of 10MHz to 40MHz and
produces six outputs of the same frequency, two with
their own Output Enable functions.
Offered in a small 3 x 3mm QFN or TSSOP package,
the PL135-67 offers the best phase noise and jitter
performance and lowest power consumption of any
comparable IC.
PACKAGE PIN CONFIGURATION
CLK4
CLK5
VDD
OE0
1312 11 10 9 8
14 7
15 6
16 5
1234
CLK3
CLK2
GND
CLK1
QFN
XIN
GND
CLK4
CLK5
VDD
OE0
CLK0
VDD
1
2
3
4
5
6
7
8
16 XOUT
15 VDD
14 CLK3
13 CLK2
12 GND
11 CLK1
10 OE1
9 GND
TSSOP
BLOCK DIAGRAM
OE0
OE1
XIN
XOUT
XTAL
OSC
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 02/14/11 Page 1




 PL135-67
PL135-67
Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:6 Oscillator Fanout Buffer
PACKAGE PIN ASSIGNMENT
Name
Package Pin #
QFN-16L (T)SSOP-16L
CLK0
1
7
VDD
2, 9, 15
5, 8, 15
GND
3, 6, 12
2, 9, 12
Type
O
P
P
OE1 4 6 I*
CLK1
CLK2
CLK3
XOUT
XIN
CLK4
CLK5
5
7
8
10
11
13
14
11 O
13 O
14 O
16 O
1I
3O
4O
OE0 14 4 I*
* Note: These pins include an internal 60kΩ pull up.
Description
Output clock
VDD connection
GND connection
Output enable (OE) input for CLK1. Internal pull-up. Pull
low to tri-state CLK1.
Output clock
Output clock
Output clock
Crystal output. Do not connect when using reference clock.
Crystal input
Output clock
Output clock
Output enable (OE) input for CLK0. Internal pull-up. Pull
low to tri-state CLK0.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 02/14/11 Page 2




 PL135-67
PL135-67
Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:6 Oscillator Fanout Buffer
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like ringing).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical value to use is 0.1F.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
(Typical buffer impedance 20Ω)
50Ω line
To CMOS Input
Crystal Tuning Circuit
Series and parallel capacitors used to fine tune the crystal load to the circuit load.
Crystal
Cst
Series Resistor
Use value to match output buffer impedance to
50Ω trace. Typical value 30Ω
XIN
1
Cpt
XOUT
8
Cpt
CST Series Capacitor, used to lower circuit load to match crystal load. Raises frequency offset.
This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator.
CPT Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers
frequency offset.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
VDD -0.5
4.6 V
Input Voltage Range
VI
-0.5
VDD+0.5
V
Output Voltage Range
VO
-0.5
VDD+0.5
V
Storage Temperature
TS -65
150 C
Ambient Operating Temperature*
-40 85 C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 02/14/11 Page 3



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