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PROGRAMMABLE DELAY. SY100EP196V Datasheet

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PROGRAMMABLE DELAY. SY100EP196V Datasheet






SY100EP196V DELAY. Datasheet pdf. Equivalent




SY100EP196V DELAY. Datasheet pdf. Equivalent





Part

SY100EP196V

Description

3.3V/5V 2.5GHz PROGRAMMABLE DELAY



Feature


Micrel, Inc. 3.3V/5V 2.5GHz PROGRAMMABL E DELAY WITH FINE TUNE CONTROL ECL Pro ® ESCYL10P0ErPo1®96V SY100EP196V FEA TURES ■ Pin-for-pin, plug-in compatib le to the ON Semiconductor MC100EP196 Maximum frequency > 2.5GHz ■ Progr ammable range: 2.2ns to 12.2ns ■ 10ps increments ■ 30ps fine tuning range ■ PECL mode operating range: VCC = 3. 0V to 5.5V with VEE = 0V ■ NECL .
Manufacture

Micrel Semiconductor

Datasheet
Download SY100EP196V Datasheet


Micrel Semiconductor SY100EP196V

SY100EP196V; mode operating range: VCC = 0V with VEE = –3.0V to –5.5V ■ Open input def ault state ■ Safety clamp on inputs A logic high on the /EN pin will for ce Q to logic low ■ D[0:10] can accep t either ECL, CMOS, or TTL inputs ■ V BB output reference voltage ■ Availab le in a 32-pin TQFP package APPLICATION S ECL Pro® DESCRIPTION The SY100EP196 V is a programmable delay line, var.


Micrel Semiconductor SY100EP196V

ying the time a logic signal takes to tr averse from IN to Q. This delay can var y from about 2.2ns to about 12.2ns. The input can be PECL, LVPECL, NECL, or LV NECL. The delay varies in discrete step s based on a control word prese .


Micrel Semiconductor SY100EP196V

.

Part

SY100EP196V

Description

3.3V/5V 2.5GHz PROGRAMMABLE DELAY



Feature


Micrel, Inc. 3.3V/5V 2.5GHz PROGRAMMABL E DELAY WITH FINE TUNE CONTROL ECL Pro ® ESCYL10P0ErPo1®96V SY100EP196V FEA TURES ■ Pin-for-pin, plug-in compatib le to the ON Semiconductor MC100EP196 Maximum frequency > 2.5GHz ■ Progr ammable range: 2.2ns to 12.2ns ■ 10ps increments ■ 30ps fine tuning range ■ PECL mode operating range: VCC = 3. 0V to 5.5V with VEE = 0V ■ NECL .
Manufacture

Micrel Semiconductor

Datasheet
Download SY100EP196V Datasheet




 SY100EP196V
Micrel, Inc.
3.3V/5V 2.5GHz PROGRAMMABLE
DELAY WITH FINE TUNE CONTROL
ECL Pro®
ESCYL10P0ErPo1®96V
SY100EP196V
FEATURES
Pin-for-pin, plug-in compatible to the ON
Semiconductor MC100EP196
Maximum frequency > 2.5GHz
Programmable range: 2.2ns to 12.2ns
10ps increments
30ps fine tuning range
PECL mode operating range: VCC = 3.0V to 5.5V
with VEE = 0V
NECL mode operating range: VCC = 0V
with VEE = –3.0V to –5.5V
Open input default state
Safety clamp on inputs
A logic high on the /EN pin will force Q to logic low
D[0:10] can accept either ECL, CMOS, or TTL inputs
VBB output reference voltage
Available in a 32-pin TQFP package
APPLICATIONS
ECL Pro®
DESCRIPTION
The SY100EP196V is a programmable delay line, varying
the time a logic signal takes to traverse from IN to Q. This
delay can vary from about 2.2ns to about 12.2ns. The input
can be PECL, LVPECL, NECL, or LVNECL.
The delay varies in discrete steps based on a control
word presented to SY100EP196V. The 10-bit width of this
latched control register allows for delay increments of
approximately 10ps. In addition, delay may be varied
continuously in about a 30ps range by setting the voltage at
the FTUNE pin.
An eleventh control bit allows the cascading of multiple
SY100EP196V devices, for a wider delay range. Each
additional SY100EP196V effectively doubles the delay range
available.
For maximum flexibility, the control register interface
accepts CMOS or TTL level signals, as well as the input
level at the IN± pins.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
CROSS REFERENCE TABLE
Clock de-skewing
Timing adjustment
Aperture centering
Micrel Semiconductor
SY100EP196VTI
SY100EP196VTITR
ON Semiconductor
MC100EP196FA
MC100EP196FAR2
TYPICAL APPLICATIONS CIRCUIT
TYPICAL PERFORMANCE
Data Signal
of Unknown Phase
CLOCK+
CLOCK–
Fine Tune Voltage
SY100EP196V
IN Q
/IN
FTUNE /Q
D[9:0]
CONTROL
LOGIC
D Q+
Flip-Flop
CK Q–
ECL Pro is a registered trademark of Micrel, Inc.
M9999-072706
hbwhelp@micrel.com or (408) 955-1690
1
12000
Delay vs. Tap
10000
8000
6000
4000
2000
0
0 200 400 600 800 1000 1200
TAP (DIGITAL WORD)
Rev.: E Amendment: /0
Issue Date: July 2006




 SY100EP196V
Micrel, Inc.
ECL Pro®
SY100EP196V
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
32 31 30 29 28 27 26 25
D8
D9
D10
IN
/IN
VBB
VEF
VCF
1
2
3
4
5
6
7
8
24 VEE
23 D0
22 VCC
21 Q
20 /Q
19 VCC
18 VCC
17 FTUNE
9 10 11 12 13 14 15 16
Part Number
SY100EP196VTI
SY100EP196VTITR(2)
SY100EP196VTG(3)
Package
Type
T32-1
T32-1
T32-1
Operating
Range
Industrial
Industrial
Industrial
SY100EP196VTGTR(2, 3) T32-1
Industrial
Package
Marking
SY100EP196V
SY100EP196V
SY100EP196V with
Pb-Free bar-line indicator
SY100EP196V with
Pb-Free bar-line indicator
Lead
Finish
Sn-Pb
Sn-Pb
Pb-Free
NiPdAu
Pb-Free
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
32-Pin TQFP (T32-1)
FUNCTIONAL BLOCK DIAGRAM
IN 0 0 0 0 0
/IN 1 1 1 1 1
512 256 128
64
32
/EN GD GD GD GD GD
FTUNE
D[9:0]
LEN
SETMIN
SETMAX
0
1
16
GD
0
1
8
GD
0
1
4
GD
0
1
2
GD
0
1
1
GD
10-bit
Latch
0
1
1
GD
Q
/Q
D[10]
VBB
VCF
VEF
Latch
M9999-072706
hbwhelp@micrel.com or (408) 955-1690
2
CASCADE
/CASCADE




 SY100EP196V
Micrel, Inc.
ECL Pro®
SY100EP196V
PIN DESCRIPTION
Pin Number
23, 25, 26, 27, 29,
30, 31, 32, 1, 2
Pin Name
D[0:9]
3 D[10]
4, 5 IN, /IN
6 VBB
7
8
9, 24, 28
10
11
VEF
VCF
VEE
LEN
SETMIN
12 SETMAX
13, 18, 19, 22
14, 15
VCC
CASCADE,
16 /EN
17
20, 21
FTUNE
Q, /Q
Pin Function
CMOS, ECL, or TTL Select Inputs: These digital control signals adjust the amount of
delay from IN to Q. Please refer to the “AC Electrical Table” (page 3) and Table 7 (page
17) for delay values. Figure 9 shows how to interface these inputs to various logic family
standards. These inputs default to logic low when left unconnected. Bit 0 is the least
significant bit, and bit 9 is the most significant bit.
CMOS, ECL, or TTL Select Input: This input latches just like D[0:9] does. It drives the
CASCADE, /CASCADE differential pair. Use only when cascading two or more
SY100EP196V to extend the range of delays required.
ECL Input: This is the signal to be delayed. If this input pair is left unconnected, this is
equivalent to a logic low input.
Voltage Output Reference: When using a single-ended logic source for IN and /IN,
connect the unused input of the differential pair to this pin. This pin can also re-bias AC-
coupled inputs to IN and /IN. When used, de-couple this pin to VCC through an 0.01µF
capacitor. Limit current sinking or sourcing to 0.5mA or less.
Voltage Output: Connect this pin to VCF when the D inputs are ECL. Refer to the “Digital
Control Logic Standard” section of the “Functional Description” to interface the D inputs to
CMOS or TTL.
Voltage Input: The voltage at this pin sets the logic transition threshold for the D inputs.
Most Negative Supply. Supply ground for PECL systems.
ECL Control Input: When logic low, the D inputs flow through. Any changes to the D inputs
reflect in the delay between IN, /IN and Q, /Q. When logic high, the logic values at D are
latched, and these latched bits determine the delay.
ECL Control Input: When logic high, the contents of the D register are reset. This sets the
delay to the minimum possible, equivalent to D[0:9] being set to 0000000000. When logic
low, the value of the D register, or the logic value of SETMAX determines the delay from
IN, /IN to Q, /Q. This input defaults to logic low when left unconnected.
ECL Control Input: When logic high and SETMIN is logic low, the contents of the D
register are set high, and the delay is set to one step greater than the maximum possible
with D[0:9] set to 1111111111. When logic low, the value of the D register, or the logic
value of SETMIN determines the delay from IN, /IN to Q, /Q. This input defaults to logic
low when left unconnected.
Most Positive Supply: Supply ground for NECL systems. Bypass to VEE with 0.1µF and
0.01µF low ESR capacitors.
100k ECL Outputs: These outputs are used when cascading two or more SY100EP196V
to /CASCADE extend the delay range required. Refer to Table 7 (page 17) for delay
values.
ECL Control Input: When set active low, Q, /Q are a delayed version of IN, /IN. When set
inactive high, IN, /IN are gated such that Q, /Q become a differential logic low. This input
defaults to logic low when left unconnected.
Voltage Control Input: By varying the voltage at this pin from VCC through VEE, the delay
may be fine tuned by approximately ±15ps. Leave pin floating if not used.
100k ECL Outputs: This signal pair is the delayed version of IN, /IN.
M9999-072706
hbwhelp@micrel.com or (408) 955-1690
3



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