Gate Arrays. AT6005 Datasheet

AT6005 Datasheet PDF, Equivalent


Part Number

AT6005

Description

Coprocessor Field Programmable Gate Arrays

Manufacture

ATMEL

Total Page 29 Pages
PDF Download
Download AT6005 Datasheet PDF


AT6005 Datasheet
Features
High-performance
– System Speeds > 100 MHz
– Flip-flop Toggle Rates > 250 MHz
– 1.2 ns/1.5 ns Input Delay
– 3.0 ns/6.0 ns Output Delay
Up to 204 User I/Os
Up to 6,400 Registers
Cache Logic® Design
– Complete/Partial In-System Reconfiguration
– No Loss of Data or Machine State
– Adaptive Hardware
Low Voltage and Standard Voltage Operation
– 5.0 (VCC = 4.75V to 5.25V)
– 3.3 (VCC = 3.0V to 3.6V)
Automatic Component Generators
– Reusable Custom Hard Macro Functions
Very Low-power Consumption
– Standby Current of 500 µA/ 200 µA
– Typical Operating Current of 15 to 170 mA
Programmable Clock Options
– Independently Controlled Column Clocks
– Independently Controlled Column Resets
– Clock Skew Less Than 1 ns Across Chip
Independently Configurable I/O (PCI Compatible)
– TTL/CMOS Input Thresholds
– Open Collector/Tristate Outputs
– Programmable Slew-rate Control
– I/O Drive of 16 mA (combinable to 64 mA)
Coprocessor
Field
Programmable
Gate Arrays
AT6000(LV)
Series
Description
AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal for
use as reconfigurable coprocessors and implementing compute-intensive logic.
Supporting system speeds greater than 100 MHz and using a typical operating current
of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive
designs. These FPGAs are designed to implement Cache Logic, which provides the
user with the ability to implement adaptive hardware and perform hardware
acceleration.
The patented AT6000 Series architecture employs a symmetrical grid of small yet
powerful cells connected to a flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is surrounded by programmable
I/O.
AT6000 Series Field Programmable Gate Arrays (continued)
Device
Usable Gates
Cells
Registers (maximum)
I/O (maximum)
Typ. Operating Current (mA)
Cell Rows x Columns
AT6002*
6,000
1,024
1,024
96
15 - 30
32 x 32
AT6003*
9,000
1,600
1,600
120
25 - 45
40 x 40
AT6005
15,000
3,136
3,136
108
40 - 80
56 x 56
AT6010
30,000
6,400
6,400
204
85 - 170
80 x 80
Obsolete: Not
Recommended for
New Design
AT6000LV Series
AT6002*
AT6003*
Atmel-0264G-FPGA-AT6000(LV)-Datasheet_042015

AT6005 Datasheet
Devices range in size from 4,000 to 30,000 usable gates,
and 1024 to 6400 registers. Pin locations are consistent
throughout the AT6000 Series for easy design migration.
High-I/O versions are available for the lower gate count
devices.
AT6000 Series FPGAs utilize a reliable 0.6 µm single-poly,
double-metal CMOS process and are 100% factory-tested.
Atmel's PC- and workstation-based Integrated Develop-
ment System is used to create AT6000 Series designs.
Multiple design entry methods are supported.
The Atmel architecture was developed to provide the high-
est levels of performance, functional density and design
flexibility in an FPGA. The cells in the Atmel array are
small, very efficient and contain the most important and
most commonly used logic and wiring functions. The cell’s
small size leads to arrays with large numbers of cells,
greatly multiplying the functionality in each cell. A simple,
high-speed busing network provides fast, efficient commu-
nication over medium and long distances.
The Symmetrical Array
At the heart of the Atmel architecture is a symmetrical array
of identical cells (Figure 1). The array is continuous and
completely uninterrupted from one edge to the other,
except for bus repeaters spaced every eight cells
(Figure 2).
In addition to logic and storage, cells can also be used as
wires to connect functions together over short distances
and are useful for routing in tight spaces.
The Busing Network
There are two kinds of buses: local and express (see
Figures 2 and 3).
Local buses are the link between the array of cells and the
busing network. There are two local buses – North-South 1
and 2 (NS1 and NS2) – for every column of cells, and two
local buses – East-West 1 and 2 (EW1 and EW2) – for
every row of cells. In a sector (an 8 x 8 array of cells
enclosed by repeaters) each local bus is connected to
every cell in its column or row, thus providing every cell in
the array with read/write access to two North-South and
two East-West buses.
Figure 1. Symmetrical Array Surrounded by I/O
2 AT6000(LV) Series
Atmel-0264G-FPGA-AT6000(LV)-Datasheet_042015


Features Datasheet pdf Features • High-performance – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay Up to 204 User I/Os • Up to 6,400 Registers • Cache Logic® Design – Complete/Partial In-System Reconfigurat ion – No Loss of Data or Machine Stat e – Adaptive Hardware • Low Voltage and Standard Voltage Operation – 5.0 (VCC = 4.75V to 5.25V) – 3.3 (VCC = 3.0V to 3.6V) • Automatic Component G enerators – Reusable Custom Hard Macr o Functions • Very Low-power Consumpt ion – Standby Current of 500 µA/ 200 µA – Typical Operating Current of 1 5 to 170 mA • Programmable Clock Opti ons – Independently Controlled Column Clocks – Independently Controlled Co lumn Resets – Clock Skew Less Than 1 ns Across Chip • Independently Config urable I/O (PCI Compatible) – TTL/CMO S Input Thresholds – Open Collector/T ristate Outputs – Programmable Slew-r ate Control – I/O Drive of 16 mA (combinable to 64 mA) Copro.
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