9FGV1004 Datasheet PDF Download, IDT





(PDF) 9FGV1004 Datasheet Download

Part Number 9FGV1004
Description Programmable PhiClock Generator
Manufacture IDT
Total Page 15 Pages
PDF Download Download 9FGV1004 Datasheet PDF

Features: Low Phase-Noise, Low-Power Programmable PhiClock™ Generator 9FGV1004 Datashe et Description The 9FGV1004 is a membe r of IDT's PhiClock™ programmable clo ck generator family. The 9FGV1004 provi des 1 copy each of 2 integer-related fr equencies, 2 copies of a fractional or spread-spectrum frequency and two copie s of the crystal reference input. Two s elect pins allow for hardware selection of the desired configuration, or two I 2C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP conf igurations as the default when operatin g in I2C mode. Four unique I2C addresse s are available, allowing easy I2C acce ss to multiple components. Typical Appl ications ▪ HPC ▪ Storage ▪ 10G/25 G Ethernet ▪ Fiber Optic Modules ▪ SSDs Output Features ▪ 4 programmable output pairs ▪ 2 integer output freq uencies and 1 fractional or spread spec trum output frequency per configuration ▪ 2 LVCMOS REF outputs ▪ 10MHz–325MHz output frequency (.

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Low Phase-Noise, Low-Power
Programmable PhiClock™ Generator
9FGV1004
Datasheet
Description
The 9FGV1004 is a member of IDT's PhiClock™ programmable
clock generator family. The 9FGV1004 provides 1 copy each of 2
integer-related frequencies, 2 copies of a fractional or
spread-spectrum frequency and two copies of the crystal
reference input. Two select pins allow for hardware selection of
the desired configuration, or two I2C bits all easy software
selection of the desired configuration. The user may configure any
one of the four OTP configurations as the default when operating
in I2C mode. Four unique I2C addresses are available, allowing
easy I2C access to multiple components.
Typical Applications
HPC
Storage
10G/25G Ethernet
Fiber Optic Modules
SSDs
Output Features
4 programmable output pairs
2 integer output frequencies and 1 fractional or spread
spectrum output frequency per configuration
2 LVCMOS REF outputs
10MHz–325MHz output frequency (LVDS or LP-HCSL), integer
configuration
10MHz–200MHz output frequency (LVCMOS), integer
configuration
10MHz–156.25MHz output frequency, fractional or spread
spectrum configuration
Block Diagram
VDDDp
OTP_VPP
Features
1.8V to 3.3V core VDD and VDDREF
Individual 1.8V to 3.3V VDDO for each output pair
Supports HCSL, LVDS and LVCMOS I/O standards
Supports LVPECL and CML logic with easy AC coupling – see
application note AN-891 for alternate terminations
HCSL utilizes IDT's LP-HCSL technology for improved
performance, lower power and higher integration:
• Programmable output impedance of 85 or 100
On-board OTP supports up to 4 complete configurations
Configuration selected via strapping pins or I2C
< 125mW at 1.8V, < 230mW at 3.3V with outputs running at
100MHz
4 programmable I2C addresses: D0/D1, D2/D3, D4/D5, D6/D7
read/write
Programmable spread spectrum modulation frequency and
amount
Supported by IDT Timing Commander™ software
Space saving 4 × 4 mm 24-VFQFPN
Key Specifications
331fs rms typical phase jitter (OUT[3:0] outputs) at 156.25MHz
(12kHz–20MHz)
PCIe Gen 1–4 compliant (spread spectrum off)
PCIe Gen 1–3 compliant (spread spectrum on)
PCIe Clocking Architectures
Supported
Common Clocked (CC)
Independent Reference without spread spectrum (SRnS)
VDDAp
XIN/CLKIN
XO
OSC
REF 1
REF 0
VDDREFp
INT
DIV
INT
PLL
INT
DIV
OUT3#
OUT3
VDDO 3
OUT2#
OUT2
VDDO 2
vSEL _I 2C#
^SEL 0/SCL
^SEL 1/SDA
^OEB
^OEA
SMBus
Engine
Factory
Configuration
FOD
(SSC)
Control Logic
Internal terminations are available when LPHCSL output format is selected .
OUT1#
OUT1
VDDO 1
OUT0#
OUT0
VDDO 0
EPAD /GND
©2018 Integrated Device Technology, Inc.
1
December 18, 2018

                    
                    






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