Synchronous DRAM. M52D2561616A Datasheet

M52D2561616A DRAM. Datasheet pdf. Equivalent

Part M52D2561616A
Description Mobile Synchronous DRAM
Feature ESMT Mobile SDRAM FEATURES  1.8V power supply  LVCMOS compatible with multiplexed address  Four b.
Manufacture ESMT
Datasheet
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ESMT Mobile SDRAM FEATURES  1.8V power supply  LVCMOS comp M52D2561616A Datasheet
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M52D2561616A
ESMT
Mobile SDRAM
FEATURES
1.8V power supply
LVCMOS compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
EMRS cycle with address
All inputs are sampled at the positive going edge of the
system clock
Special function support
- PASR (Partial Array Self Refresh)
- TCSR (Temperature Compensated Self Refresh)
- DS (Driver Strength)
DQM for masking
Auto & self refresh
64ms refresh period (8K cycle)
M52D2561616A (2F)
4M x 16 Bit x 4 Banks
Mobile Synchronous DRAM
ORDERING INFORMATION
Product ID
Max Freq. Package Comments
M52D2561616A-5BG2F 200MHz 54 Ball FBGA Pb-free
M52D2561616A-6BG2F 166MHz 54 Ball FBGA Pb-free
M52D2561616A-7BG2F 143MHz 54 Ball FBGA Pb-free
GENERAL DESCRIPTION
The M52D2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304
words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies
allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
BALL CONFIGURATION (TOP VIEW)
(BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
12 3456 789
A VSS DQ15 VSSQ
VDDQ DQ0 VDD
B DQ14 DQ13 VDDQ
VSSQ DQ2 DQ1
C DQ12 DQ11 VSSQ
VDDQ DQ4 DQ3
D DQ10 DQ9 VDDQ
VSSQ DQ6 DQ5
E
DQ8 NC
VSS
VDD LDQM DQ7
F UDQM CLK CKE
G
A12 A11
A9
CAS RAS WE
BA0 BA1
CS
H A8 A7 A6
J
VSS A5
A4
A0 A1 A10
A3 A2 VDD
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2014
Revision: 1.1
1/46



M52D2561616A
ESMT
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
Clock
Generator
Address
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Column
Address
Buffer
&
Refresh
Counter
M52D2561616A (2F)
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
L(U)DQM
DQ
BALL FUNCTION DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A12
BA0 , BA1
RAS
CAS
WE
L(U)DQM
DQ0 ~ DQ15
VDD / VSS
VDDQ / VSSQ
NC
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~ RA12, column address : CA0~CA8
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2014
Revision: 1.1
2/46





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