ESMT
(Prliminary)
M53D1G1664A
Mobile DDR SDRAM
16M x16 Bit x 4 Banks
Mobile DDR SDRAM
Features
JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized.
Differential clock inputs (CLK and CLK )
Four bank operation CAS Latency : 2, 3 Burst Type...
