DDR3 SDRAM. M15F5121632A Datasheet

M15F5121632A SDRAM. Datasheet pdf. Equivalent

Part M15F5121632A
Description DDR3 SDRAM
Feature ESMT DDR3 SDRAM (Preliminary) Feature Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075.
Manufacture ESMT
Datasheet
Download M15F5121632A Datasheet

ESMT DDR3 SDRAM (Preliminary) Feature Interface and Power M15F5121632A Datasheet
Recommendation Recommendation Datasheet M15F5121632A Datasheet




M15F5121632A
ESMT
DDR3 SDRAM
(Preliminary)
Feature
Interface and Power Supply
˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)
JEDEC DDR3 Compliant
˗ 8n Prefetch Architecture
˗ Differential Clock (CK/ CK ) and Data Strobe
(DQS/ DQS )
˗ Double-data rate on DQs, DQS and DM
Data Integrity
˗ Auto Refresh and Self Refresh Modes
Power Saving Mode
˗ Partial Array Self Refresh(PASR)
˗ Power Down Mode
Signal Integrity
˗ Configurable DS for system compatibility
˗ Configurable On-Die Termination
˗ ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240 ohm ± 1%)
Signal Synchronization
M15F5121632A
4M x 16 Bit x 8 Banks
DDR3 SDRAM
˗ Write Leveling via MR settings
˗ Read Leveling via MPR
Programmable Functions
˗ CAS Latency (5/6/7/8/9/10/11/12/13)
˗ CAS Write Latency (5/6/7/8/9)
˗ Additive Latency (0/CL-1/CL-2)
˗ Write Recovery Time (5/6/7/8/10/12/14/16)
˗ Burst Type (Sequential/Interleaved)
˗ Burst Length (BL8/BC4/BC4 or 8 on the fly)
˗ Self Refresh Temperature Range(Normal/Extended)
˗ Output Driver Impedance (34/40)
˗ On-Die Termination of RTT_Nom(20/30/40/60/120)
˗ On-Die Termination of RTT_WR(60/120)
˗ Precharge Power Down (slow/fast)
Ordering Information
Product ID
Max Freq.
M15F5121632A–EFBG
M15F5121632A–DEBG
1066MHz
933MHz
VDD
1.5V
1.5V
Data Rate
(CL-tRCD-tRP)
DDR3-2133 (14-14-14)
DDR3-1866 (13-13-13)
Package Comments
96 ball BGA
96 ball BGA
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc
Publication Date : May 2018
Revision : 0.1
1/160



M15F5121632A
ESMT
(Preliminary)
M15F5121632A
Description
The 512Mb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation. It is internally
configured as an eight-bank DRAM.
The 512Mb chip is organized as 4Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed
double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized
with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.
DDR3 SDRAM Addressing
Configuration
32Mb x 16
# of Bank
8
Bank Address
BA0 – BA2
Auto precharge
A10 / AP
BL switch on the fly
Row Address
A12 / BC
A0 – A11
Column Address
A0 – A9
Page size
2KB
Note:
Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is
registered. Page size is per bank, calculated as follows:
Page size = 2 COLBITS * ORG / 8
where
COLBITS = the number of column address bits
ORG = the number of I/O (DQ) bits
Elite Semiconductor Memory Technology Inc
Publication Date : May 2018
Revision : 0.1
2/160





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)