X84161 EEPROM Datasheet

X84161 Datasheet, PDF, Equivalent


Part Number

X84161

Description

uPort Saver EEPROM

Manufacture

Xicor

Total Page 17 Pages
Datasheet
Download X84161 Datasheet


X84161
APPLICATION NOTE
AVAILABLE
AN95 • AN103 • AN107
16K/64K
X84161/641
µPort Saver EEPROM
MPSEEPROM
FEATURES
• Up to 10MHz data transfer rate
• 25ns Read Access Time
• Direct interface to microprocessors and micro-
controllers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low power CMOS
—2.5V–5.5V and 5V ±10% versions
—Standby current less than 1µA
—Active current less than 1mA
• Byte or page write capable
—32-byte page write mode
• Typical nonvolatile write cycle time: 2ms
• High reliability
—100,000 endurance cycles
—Guaranteed data retention: 100 years
• Small packages options
—8-lead mini-DIP package
—8-lead SOIC package
—8, 20-lead TSSOP package
BLOCK DIAGRAM
Ports
Saved
System Connection
µP
µC
DSP
ASIC
RISC
P0/CS
P1/CLK
P2/DI
P3/DO
A15
A0
D7
D0
OE
WE
DESCRIPTION
The µPort Saver memories need no serial ports or
special hardware and connect to the processor mem-
ory bus. Replacing bytewide data memory, the µPort
Saver uses bytewide memory control functions, takes
a fraction of the board space and consumes much less
power. Replacing serial memories, the µPort Saver
provides all the serial benefits, such as low cost, low
power, low voltage, and small package size, while
releasing I/Os for more important uses.
The µPort Saver memory outputs data within 25ns of
an active read signal. This is less than the read access
time of most hosts and provides “no-wait-state” opera-
tion. This prevents bottlenecks on the bus. With rates
to 10MHz, the µPort Saver supplies data faster than
required by most host read cycle specifications. This
eliminates the need for software NOPs.
The µPort Saver memories communicate over one line
of the data bus using a sequence of standard bus read
and write operations. This “bit serial” interface allows
the µPort Saver to work well in 8-bit, 16-bit, 32-bit, and
64-bit systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
Internal Block Diagram
MPS
WP H.V. Generation
Timing & Control
CE
Command
I/O Decode
OE
and
Control
Logic
WE
X
DEC
EEPROM
Array
8K x 8
2K x 8
Y Decode
Data Register
REV 1.0 6/30/00
www.xicor.com
Characteristics subject to change without notice. 1 of 17

X84161
X84161/641
PIN CONFIGURATIONS
8-Lead PDIP/SOIC
CE 1
8
I/O 2 X84161 7
WP 3 X84641 6
VSS
4
5
VCC
NC
OE
WE
8-Lead TSSOP
NC 1
8
VCC
CE
2
3
7
X84161 6
I/O 4
5
OE
WE
WP
VSS
20-Lead TSSOP
NC 1
20 NC
NC 2
19 NC
CE 3
18 VCC
I/O 4
17 NC
NC 5 X84641 16 NC
NC 6
15 NC
NC 7
14 NC
WP 8
13 OE
VSS 9
12 WE
NC 10
11 NC
PIN NAMES
Pin Description
I/O Data Input/Output
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
WP Write Protect Input
VCC Supply Voltage
VSS Ground
NC No Connect
PACKAGE SELECTION GUIDE
84161
84641
8-Lead PDIP
8-Lead SOIC
8-Lead TSSOP
8-Lead XBGA
8-Lead PDIP
8-Lead SOIC
20-Lead TSSOP
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese-
lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
device is in the standby power mode.
Output Enable (OE)
The Output Enable input must be LOW to enable the
output buffer and to read data from the device on the I/O
line.
Write Enable (WE)
The Write Enable input must be LOW to write either
data or command sequences to the device.
Data In/Data Out (I/O)
Data and command sequences are serially written to
or serially read from the device through the I/O pin.
Write Protect (WP)
When the Write Protect input is LOW, nonvolatile writes
to the device are disabled. When WP is HIGH, all func-
tions, including nonvolatile writes, operate normally. If a
nonvolatile write cycle is in progress, WP going LOW
will have no effect on the cycle already underway, but
will inhibit any additional nonvolatile write cycles.
DEVICE OPERATION
The X84161/641 are serial EEPROMs designed to
interface directly with most microprocessor buses.
Standard CE, OE, and WE signals control the read and
write operations, and a single l/O line is used to send
and receive data and commands serially.
Data Timing
Data input on the l/O line is latched on the rising edge
of either WE or CE, whichever occurs first. Data output
on the l/O line is active whenever both OE and CE are
LOW. Care should be taken to ensure that WE and OE
are never both LOW while CE is LOW.
Read Sequence
A read sequence consists of sending a 16-bit address
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and
CE LOW, OE HIGH) to the part without a read cycle
between the write cycles. The address is sent serially,
REV 1.0 6/30/00
www.xicor.com
Characteristics subject to change without notice. 2 of 17


Features Obsolete Product APPLICATION NOTE AVAIL ABLE AN95 • AN103 • AN107 16K/64K X84161/641 µPort Saver EEPROM MPS™ EEPROM FEATURES • Up to 10MHz data t ransfer rate • 25ns Read Access Time • Direct interface to microprocessors and micro- controllers —Eliminates I /O port requirements —No interface gl ue logic required —Eliminates need fo r parallel to serial converters • Low power CMOS —2.5V–5.5V and 5V ±10% versions —Standby current less than 1µA —Active current less than 1mA Byte or page write capable —32-byte page write mode • Typical nonvolatil e write cycle time: 2ms • High reliab ility —100,000 endurance cycles —Gu aranteed data retention: 100 years • Small packages options —8-lead mini-D IP package —8-lead SOIC package —8, 20-lead TSSOP package BLOCK DIAGRAM Ports Saved System Connection µP µC DSP ASIC RISC P0/CS P1/CLK P2/DI P3/DO A15 A0 D7 D0 OE WE DESCRIPTION The Port Saver memories need no serial ports or special hardware a.
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