CPU Supervisor. X40626 Datasheet

X40626 Supervisor. Datasheet pdf. Equivalent

Part X40626
Description 8K x 8 Bit Dual Voltage CPU Supervisor
Feature DATASHEET X40626 64K, 8K x 8 Bit Dual Voltage CPU Supervisor with 64K Serial EEPROM FN8119 Rev 0.0.
Manufacture Renesas
Datasheet
Download X40626 Datasheet

Preliminary Information 64K X40626 Dual Voltage CPU Supervi X40626 Datasheet
DATASHEET X40626 64K, 8K x 8 Bit Dual Voltage CPU Superviso X40626 Datasheet
Recommendation Recommendation Datasheet X40626 Datasheet




X40626
DATASHEET
X40626
64K, 8K x 8 Bit Dual Voltage CPU Supervisor with 64K Serial EEPROM
FN8119
Rev 0.00
March 28, 2005
FEATURES
• Dual voltage monitoring
—V2Mon operates independent of VCC
• Watchdog timer with selectable timeout intervals
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—User programmable VTRIP threshold
—Reset signal valid to VCC=1V
• Low power CMOS
—20µA max standby current, watchdog on
—1µA standby current, watchdog OFF
• 64Kbits of EEPROM
—64 byte page size
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lockprotection
• 400kHz 2-wire interface
—Slave addressing supports up to 4 devices on
the same bus
• 2.7V to 5.5V power supply operation
• Available Packages
—14-lead SOIC
—14-lead TSSOP
DESCRIPTION
The X40626 combines four popular functions, Power-on
Reset Control, Watchdog Timer, Dual Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to stabi-
lize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time-
out interval, the device activates the RESET signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after cycling
the power.
BLOCK DIAGRAM
V2MON
WP
SDA
SCL
S0
S1
VCC
V2 Monitor
Logic
+
VTRIP2
-
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Protect Logic
Status
Register
64KB
EEPROM
Array
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
VTRIP
+
-
Power-on and
Low Voltage
Reset
Generation
V2FAIL
RESET
FN8119 Rev 0.00
March 28, 2005
Page 1 of 22



X40626
X40626
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the set minimum VCC trip point.
RESET is asserted until VCC returns to proper operating
level and stabilizes. Four industry standard Vtrip thresholds
are available. However, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom require-
ments or to fine-tune the threshold for applications requir-
ing higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block LockProtection. The
array is internally organized as 64 bytes per page. The
device features an 2-wire interface and software protocol
allowing operation on an I2C bus.
PIN FUNCTION
The device utilizes Intersil’s proprietary Direct Writecell,
providing a minimum endurance of 100,000 page write
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
14 Pin SOIC/TSSOP
NC
S0
S1
NC
RESET
NC
VSS
1
2
3
4
5
6
7
14 VCC
13 NC
12 WP
11 V2MON
10 V2FAIL
9 SCL
8 SDA
Pin
1, 4, 6, 13
2
3
5
7
8
9
10
11
12
14
Name
NC
S0
S1
RESET
VSS
SDA
SCL
V2FAIL
V2MON
WP
VCC
Function
No Internal Connections
Device Select Input
Device Select Input
Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC
falls below the minimum VCC sense level. It will remain active until VCC rises above the mini-
mum VCC sense level for typically 200ms. RESET goes active if the Watchdog Timer is
enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time-out
period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET goes
active on power-up and remains active for typically 200ms after the power supply
stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This
pin requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time-out
period results in RESET going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2
and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on
this pin. This circuit works independently from the Low VCC reset and battery switch circuits.
Connect V2FAIL to VSS when not used.
V2 Voltage
goes LOW.
Monitor Input. When
This input can monitor
the
an
V2MON input is less than
unregulated power supply
twhiethVaTnRIePx2tevornltaalgree,sVis2toFrAIL
divider or can monitor a second power supply with no external components. Connect V2MON
to VSS or VCC when not used. There is no hysteresis in the V2MON comparator circuits.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control reg-
ister.
Supply Voltage
FN8119 Rev 0.00
March 28, 2005
Page 2 of 22





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