Battery Authentication. ISL9206A Datasheet

ISL9206A Authentication. Datasheet pdf. Equivalent

ISL9206A Datasheet
Recommendation ISL9206A Datasheet
Part ISL9206A
Description FlexiHash+ For Battery Authentication
Feature ISL9206A; DATASHEET ISL9206A FlexiHash+™ For Battery Authentication The ISL9206A is a highly cost-effective .
Manufacture Renesas
Datasheet
Download ISL9206A Datasheet




Renesas ISL9206A
DATASHEET
ISL9206A
FlexiHash+™ For Battery Authentication
The ISL9206A is a highly cost-effective fixed-secret hash
engine based on Intersil’s second generation FlexiHash™
technology. The device authentication is achieved through a
challenge-response scheme customized for low-cost
applications, where cloning via eavesdropping without
knowledge of the device’s secret code is not economically
viable. When used for its intended applications, the
ISL9206A offers the same level of effectiveness as other
significantly more expensive high-maintenance hash
algorithm and authentication schemes.
The ISL9206A has a wide operating voltage range, and is
suitable for direct powering from a 1-cell Li-ion/Li-Poly or a
3-cell series NiMH battery pack. The ISL9206A can also be
powered by the XSD bus when the bus pull-up voltage is
3.3V or higher. The device connects directly to the cell
terminals of a battery pack, and includes on-chip voltage
regulation circuit, POR, and a non-crystal based oscillator for
bus timing reference.
Communication with the host is achieved through a single
wire XSD interface (a light-weight subset of Intersil’s ISD bus
interface). The XSD bus is compatible for use with serial ports
offered by all 8250 compatible UART’s or a single GPIO
(General Purpose Input and Output) pin of a microprocessor.
A clone prevention solution utilizing the ISL9206A offers
safety and revenue protection at the lowest cost and power,
and is suitable for protection against after-market
replacement for a wide variety of low-cost applications.
Ordering Information
PART NUMBER PART
TEMP.
PACKAGE PKG.
(Note)
MARKING RANGE (°C) (Pb-free) DWG. #
ISL9206ADHZ-T* 206A
-25 to +85 5 Ld SOT-23 P5.064
ISL9206ADRTZ-T* 06A
-25 to +85 8 Ld 2x3 TDFN L8.2x3A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinouts
ISL9206A
(8 LD 2X3 TDFN)
TOP VIEW
ISL9206A
(5 LD SOT-23)
TOP VIEW
VSS 1
NC 2
NC 3
VDD 4
8 XSD
7 NC
6 NC
5 TIO
VSS 1
NC 2
VDD 3
5 XSD
4 TIO
FN6651
Rev 1.00
July 30, 2008
Features
• Challenge-response based authentication scheme using
32-Bit challenge code and 8-Bit authentication code.
• Fast and flexible authentication process. Multi-pass
authentication can be used to achieve the highest security
level if necessary.
• 16x8 OTP ROM stores up to three sets of 32-Bit
host-selectable secrets with additional programmable
memory for storage of up to 48-Bits of ID code and/or pack
information.
• FlexiHash+™ engine uses two sets of 32-Bit secrets for
authentication code generation.
• Non-unique mapping of the secret key to an 8-Bit
authentication code maximizes hacking difficulty due to
need for exhaustive key search (superior to SHA-1).
• Supports 1-cell Li-ion/Li-Poly and 3-cell series NiMH
battery packs (2.6V ~ 4.8V operation), or powered by the
XSD bus.
• XSD single-wire host bus interface communicates with all
8250-compatible UART’s or a single GPIO. Supports CRC
on read data and transfer bit-rate up to 23kbps.
• True “Zero Power” Sleep mode (automatically entered
after a bus inactivity time-out period)
• 5 Ld SOT-23 or 8 Ld TDFN (2mmx3mm) packages
• -25°C to +85°C operating temperature range
• Pb-free (RoHS compliant)
Applications
• Battery Pack Authentication
• Printer Cartridges
• Add-on Accessories
• Other Non-Monetary Authentication Applications
Related Literature
• Application Note AN1165 “ISL6296 Evaluation Kit”
• Application Note AN1167 “Implementing XSD Host Using
a GPIO”
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
FN6651 Rev 1.00
July 30, 2008
Page 1 of 17



Renesas ISL9206A
ISL9206A
Absolute Maximum Ratings (Reference to GND)
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDD + 0.5V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .4000V
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .400V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000V
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-25°C to +85°C
Thermal Information
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
SOT-23 Package (Note 1) . . . . . . . . . . 200
N/A
2x3 TDFN Package (Notes 2, 3) . . . . .
70
10.5
Maximum Junction Temperature (Plastic Package) . . . . . . . +125°C
Maximum Storage Temperature Range . . . . . . . . . .-40°C to +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise noted, all parameters are established over the operational supply voltage and temperature
range of the device as follows: TA = -25°C to +85°C; VDD = 2.6V to 4.8V; Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
MAX UNITS
DC CHARACTERISTICS
Supply Voltage
VDD
During normal operation
During OTP ROM programming
2.6 -
2.8 -
4.8 V
4.8 V
Run Mode Supply Current
(Exclude I/O Current)
Sleep Mode Supply Current
OTP Programming Mode Supply Current
Internal Regulated Supply Voltage
Internal OTP ROM Programming Voltage
POR Release Threshold
POR Assertion Threshold
XSD PIN CHARACTERISTICS
IDD
IDDS
IDDP
VRG
VPP
VPOR+
VPOR-
VDD = 4.2V
VDD = 4.8V
VDD = 1.5V
VDD = 4.2V, XSD pin floating
For ~ 1.8ms duration per write operation
Observable only in test mode
Observable only in test mode
- 38
55 µA
- 40
65 µA
5.0 8.0 µA
- 0.15 0.5 µA
- 250 500 µA
2.3 2.5 2.7 V
11 12 13 V
1.9 2.2 2.4 V
1.5 1.8 2.1 V
XSD Input Low Voltage
XSD Input High Voltage
XSD Input Hysteresis
XSD Internal Pull-down Current
XSD Output Low Voltage
XSD Input Transition Time
XSD Output Fall Time
XSD Pin Capacitance
VIL
VIH
VHYS
IPD
VOL
tX
tF
CPIN
VDD = 2.6V
VDD = 4.2V
VDD = 4.8V
IOL = 1mA
10% to 90% transition time
90% to 10%, CLOAD = 12pF
-0.4 -
0.5 V
1.5 - VDD + 0.4V V
- 400
- mV
- 0.8
- µA
- 1.2 2.0 µA
- 1.8 2.5 µA
- - 0.4 V
--
2 µs
--
50 ns
-6
- pF
FN6651 Rev 1.00
July 30, 2008
Page 2 of 17



Renesas ISL9206A
ISL9206A
Electrical Specifications
Unless otherwise noted, all parameters are established over the operational supply voltage and temperature
range of the device as follows: TA = -25°C to +85°C; VDD = 2.6V to 4.8V; Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
MAX UNITS
XSD BUS TIMING CHARACTERISTICS (Refer to XSD Bus Symbol Timing Definitions Tables beginning on page 8)
Programming Bit Rate
x = 0.5 to 4
2.89 -
23.12 kHz
XSD Input De-glitch Time
tWDG Pulse width narrower than the de-glitch time will not
cause the device to wake up
7
-
20 µs
Device Wake-up Time
tWKE From falling-edge of break command issued by host to 130
160
200
µs
falling-edge of break command returned by device
Device Sleep Wait Time
tSLP From when the ‘11’ Opcode is detected to the shut-off
of the internal regulator
4
-
- µs
Auto-Sleep Time-out Period
tASLP From the last transition detected on the XSD bus to the
device going into sleep mode
-
1
-s
OTP ROM Write Time
tEEW From the last BT of the 2nd write data frame to when
-
1.8
1.9 ms
device is ready to accept the next instruction
Hash Calculation Time
tHASH
From the last BT of the Challenge Code Word from the
host to the Authentication Code being available for
read
-
1
- BT
Soft-Reset Time
tSRST
From the last BT of the Soft-Reset instruction issued
by the host to the falling-edge of break command
returned by device
-
-
30 µs
Pin Descriptions
SOT-23
TDFN
PIN NUMBER PIN NUMBER
11
2 2, 3, 6, 7
34
45
58
PIN NAME
VSS
NC
VDD
TIO
XSD
DESCRIPTION
System ground.
No connection.
Supply voltage.
Production test I/O pin. Used only during production testing. Must be left floating during
normal operation.
Communication bus with weak internal pull-down to VSS. This pin is a Schmitt-trigger input
and an open-drain output. An appropriate pull-up resistor is required on the host side.
FN6651 Rev 1.00
July 30, 2008
Page 3 of 17







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