32-bit CPU. S32R274 Datasheet

S32R274 CPU. Datasheet pdf. Equivalent

S32R274 Datasheet
Recommendation S32R274 Datasheet
Part S32R274
Description 32-bit CPU
Feature S32R274; NXP Semiconductors Data Sheet: Technical Data Document Number S32R274 Rev. 4, 05/2018 S32R274 Data.
Manufacture NXP
Datasheet
Download S32R274 Datasheet




NXP S32R274
NXP Semiconductors
Data Sheet: Technical Data
Document Number S32R274
Rev. 4, 05/2018
S32R274 Data Sheet
Features
• On-chip modules available within the device include
the following features:
• Safety core: Power Architecture® e200Z4 32-bit CPU
with checker core
• Dual issue computation cores: Power Architecture®
e200Z7 32-bit CPU
• 2 MB on-chip code flash (FMC flash) with ECC
• 1.5 MB on-chip SRAM with ECC
• RADAR processing
– Signal Processing Toolbox (SPT) for RADAR signal
processing acceleration
– Cross Timing Engine (CTE) for precise timing
generation and triggering
– Waveform generation module (WGM) for chirp
ramp generation
– 4x 12-bit ΣΔ-ADC with 10 MSps
– One DAC with 10 MSps
– MIPICSI2 interface to connect external ADCs
• Memory Protection
– Each core memory protection unit provides 24
entries
– Data and instruction bus system memory protection
unit (SMPU) with 16 region descriptors each
– Register protection
• Clock Generation
– 40 MHz external crystal (XOSC)
– 16 MHz Internal oscillator (IRCOSC)
– Dual system PLL with one frequency modulated
phase-locked loop (FMPLL)
– Low-jitter PLL to ΣΔ-ADC and DAC clock
generation (not supported on SC66760x devices)
• Functional Safety
– Enables up to ASIL-D applications
– FCCU for fault collection and fault handling
– MEMU for memory error management
– Safe eDMA controller
– Self-Test Control Unit (STCU2)
– Error Injection Module (EIM)
– On-chip voltage monitoring
– Clock Monitor Unit (CMU)
S32R274
• Security
– Cryptographic Security Engine (CSE2)
– Supports censorship and life-cycle management
• Timers
– Two Periodic Interval Timers (PIT) with 32-bit
counter resolution
– Three System Timer Module (STM)
– Three Software Watchdog Timers (SWT)
– Two eTimer modules with 6 channels each
– One FlexPWM module for 12 PWM signals
• Communication Interfaces
– Two Serial Peripheral interface (SPI) modules
– One LINFlexD module
– Two inter-IC communication interface (I2C)
modules
– One dual-channel FlexRay module with 128
message buffers
– Three FlexCAN modules with configurable buffers -
CAN FD optionally supported on 2 FlexCAN
modules
– One ENET MAC supporting MII/RMII/RGMII
interface
– ZipWire high-speed serial communication
• Debug Functionality
– 4-pin JTAG interface and Nexus/Aurora interface
for serial high-speed tracing
– e200Z7 core and e200Z4 core: Nexus development
interface (NDI) per IEEE-ISTO 5001-2012 Class 3+
• Two analog-to-digital converters (SAR ADC)
– Each ADC supports up to 16 input channels
– Cross Trigger Unit (CTU)
• On-chip voltage DC/DC regulator for core clock
(VREG)
• Two Temperature Sensors (TSENS)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.



NXP S32R274
S32R274 Data Sheet, Rev. 4, 05/2018
2 NXP Semiconductors



NXP S32R274
Table of Contents
1 Introduction........................................................................................ 4
8.4 Data retention vs program/erase cycles...................................40
1.1 Family comparison..................................................................4
8.5 Flash memory AC timing specifications.................................40
1.2 Feature list............................................................................... 5
8.6 Flash memory read wait-state and address-pipeline control
1.3 Block diagram......................................................................... 9
settings.....................................................................................41
2 Ordering parts.....................................................................................9
9 Communication modules................................................................... 42
2.1 Determining valid orderable parts...........................................9
9.1 Ethernet switching specifications............................................42
3 Part identification............................................................................... 10
9.2 FlexRay timing parameters..................................................... 47
3.1 Description.............................................................................. 10
9.3 LVDS Fast Asynchronous Transmission (LFAST) electrical
3.2 Fields....................................................................................... 10
characteristics.......................................................................... 50
4 General............................................................................................... 11
9.4 Serial Peripheral Interface (SPI) timing specifications........... 54
4.1 Absolute maximum ratings..................................................... 11
9.5 LINFlexD timing specifications..............................................59
4.2 Operating conditions............................................................... 13
9.6 I2C timing .............................................................................. 59
4.3 Supply current characteristics................................................. 15
10 Debug modules...................................................................................60
4.4 Voltage regulator electrical characteristics............................. 16
10.1 JTAG/CJTAG interface timing .............................................. 60
4.5 Electromagnetic Compatibility (EMC) specifications............ 20
10.2 Nexus Aurora debug port timing.............................................63
4.6 Electrostatic discharge (ESD) characteristics......................... 20
11 WKUP/NMI timing specifications.....................................................64
5 I/O Parameters....................................................................................21
12 External interrupt timing (IRQ pin)................................................... 65
5.1 I/O pad DC electrical characteristics ......................................21
13 Temperature sensor electrical characteristics.....................................65
5.2 I/O pad AC specifications....................................................... 22
14 Radar module..................................................................................... 66
5.3 Aurora LVDS driver electrical characteristics........................ 23
14.1 MIPICSI2 D-PHY electrical and timing specifications.......... 66
5.4 Reset pad electrical characteristics..........................................24
14.2 MIPICSI2 Disclaimer..............................................................69
6 Peripheral operating requirements and behaviours............................ 26
15 Thermal Specifications.......................................................................71
6.1 Clocks and PLL Specifications............................................... 26
15.1 Thermal characteristics........................................................... 71
7 Analog modules................................................................................. 29
16 Packaging........................................................................................... 73
7.1 ADC electrical characteristics.................................................29
17 Reset sequence................................................................................... 73
7.2 Sigma Delta ADC electrical characteristics............................ 33
17.1 Reset sequence duration.......................................................... 74
7.3 DAC electrical specifications..................................................37
17.2 Reset sequence description......................................................74
8 Memory modules............................................................................... 38
18 Power sequencing requirements.........................................................76
8.1 Flash memory program and erase specifications.................... 38
19 Pinouts................................................................................................77
8.2 Flash memory Array Integrity and Margin Read
19.1 Package pinouts and signal descriptions................................. 77
specifications........................................................................... 39
20 Revision History.................................................................................77
8.3 Flash memory module life specifications................................39
NXP Semiconductors
S32R274 Data Sheet, Rev. 4, 05/2018
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