Flash Memory. AT49F040 Datasheet

AT49F040 Datasheet PDF, Equivalent


Part Number

AT49F040

Description

5-volt-only in-system Flash Memory

Manufacture

ATMEL Corporation

Total Page 13 Pages
PDF Download
Download AT49F040 Datasheet PDF


AT49F040 Datasheet
Features
Single-voltage Operation
– 5V Read
– 5V Reprogramming
Fast Read Access Time – 55 ns
Internal Program Control and Timer
16-Kbyte Boot Block with Lockout
Fast Erase Cycle Time 10 seconds
Byte-by-byte Programming 50 µs/Byte
Hardware Data Protection
DATA Polling for End of Program Detection
Low Power Dissipation
50 mA Active Current
100 µA CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49F040 is a 5-volt-only in-system Flash Memory. Its 4 megabits of memory is
organized as 524,288 words by 8 bits. Manufactured with Atmels advanced nonvola-
tile CMOS technology, the device offers access times to 55 ns with power dissipation
of just 275 mW over the commercial temperature range. When the device is dese-
lected, the CMOS standby current is less than 100 µA.
The device contains a user-enabled boot blockprotection feature. The AT49F040
locates the boot block at lowest order addresses (bottom boot).
(continued)
4-megabit
(512K x 8)
5-volt Only
Flash Memory
AT49F040
Pin Configurations
Pin Name
A0 - A18
CE
OE
WE
I/O0 - I/O7
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
TSOP Top View
Type 1
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 OE
31 A10
30 CE
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
DIP Top View
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 WE
30 A17
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
PLCC Top View
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
Rev. 0998D03/01
1

AT49F040 Datasheet
To allow for simple in-system reprogrammability, the
AT49F040 does not require high input voltages for pro-
gramming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM.
Reprogramming the AT49F040 is performed by erasing the
entire 4 megabits of memory and then programming on a
byte-by-byte basis. The byte programming time is a fast
50 µs. The end of a program cycle can be optionally
detected by the DATA polling feature. Once the end of a
byte program cycle has been detected, a new access for a
read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles.
The optional 16K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
VCC
GND
OE
WE
CE
ADDRESS
INPUTS
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
MAIN MEMORY
(496K BYTES)
OPTIONAL BOOT
BLOCK (16K BYTES)
7FFFFH
04000H
03FFFH
00000H
Device Operation
READ: The AT49F040 is accessed like an EPROM. When
CE and OE are low and WE is high, the data stored at the
memory location determined by the address pins is
asserted on the outputs. The outputs are put in the
high impedance state whenever CE or OE is high. This
dual-line control gives designers flexibility in preventing bus
contention.
ERASURE: Before a byte can be reprogrammed, the 512K
bytes memory array (or 496K bytes if the boot block fea-
tured is used) must be erased. The erased state of the
memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DATA polling feature may also be used to indi-
cate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
00000H to 03FFFH.
2 AT49F040


Features Datasheet pdf Features • Single-voltage Operation 5V Read – 5V Reprogramming • Fast Read Access Time – 55 ns • Interna l Program Control and Timer • 16-Kbyt e Boot Block with Lockout • Fast Eras e Cycle Time – 10 seconds • Byte-by -byte Programming – 50 µs/Byte • H ardware Data Protection • DATA Pollin g for End of Program Detection • Low Power Dissipation – 50 mA Active Curr ent – 100 µA CMOS Standby Current Typical 10,000 Write Cycles Descripti on The AT49F040 is a 5-volt-only in-sys tem Flash Memory. Its 4 megabits of mem ory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advan ced nonvolatile CMOS technology, the de vice offers access times to 55 ns with power dissipation of just 275 mW over t he commercial temperature range. When t he device is deselected, the CMOS stand by current is less than 100 µA. The de vice contains a user-enabled “boot bl ock” protection feature. The AT49F040 locates the boot block at lowest order addresses (“bottom bo.
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