Interface Adapter/Timer. R65C24 Datasheet

R65C24 Adapter/Timer. Datasheet pdf. Equivalent

Part R65C24
Description Peripleral Interface Adapter/Timer
Feature €» Rockwell R65C24 R65C24 Peripheral Interface Adapter/Timer (PIAT) DESCRIPTION The R65C24 Periphe.
Manufacture Rockwell
Datasheet
Download R65C24 Datasheet



R65C24
€»
Rockwell
R65C24
R65C24
Peripheral Interface Adapter/Timer (PIAT)
DESCRIPTION
The R65C24 Peripheral Interface A dapter/T im er (PIAT) is
designed to solve a broad range of peripheral control problems in
the implementation of microcomputer systems. This device allows
a very effective tra d e o ff between software and hardware by pro­
viding significant capability and flexibility in a low cost chip. When
coupled with the power and speed of the R6500, R6500/* or
R65COO family of microprocessors, the R65C24 allows implemen­
tation of very complex systems at a minimum overall cost.
Control of peripheral devices is handled primarily through two
8-bit bidirectional ports. Each of these lines can be programmed
to act as either an input or an output, in addition, four peripheral
control/interrupt input lines are provided. These lines can be
used to interrupt the processor or to “ handshake” data between
the processor and a peripheral device.
TTie PIAT also contains one 16-bit Counter/Tim er comprised of
a 16-bit counter, two 8-bit latches associated with the counter,
and an 8-bit snapshot latch for the upper half of the counter.
A counter mode control register, under software direction, selects
any one of eight counter modes of operation, and the status
register contains an underflow flag to report counter time-out.
A maskable interrupt request allows immediate CPU notifica­
tion upon counter time-out.
FEATURES
• Low power CMOS N-wefl sillicon gate technology
• Two 8-bit bidirectional I/O ports with individual data direction
control
• Programmable 16-bit Counter/Timer with eight modes of
operation
• Three 8-bit latches associated with the Counter/Timer
• Selectable divide-by-sixteen prescaler for all modes
• Automatic "H andshake" control of data transfers
• Three interrupts with program control
— Port A
— Port B
— Counter/Timer
1, 2, 3, and 4 MHz versions
Commercial and industrial temperature range versions
Wide variety of packages
— 40-pin plastic and ceramic DIP
— 44-pin plastic leaded chip carrier (PLCC)
Single + 5 Vdc power requirement
Compatible with the R6500, R 8500/' and R65C00 family of
microprocessors
V» C 1
PAO L 2
PA1 L 3
PA2 C 4
PA3 C 5
PA4 C 6
PA5 c 7
PA6 c B
PA7 c 9
PBO c 10
PB 1 L 11
P B 2 c 12
P B 3 c 13
P B 4 c 14
P B 5 c 15
P B 6 c 16
PB7 c 17
CB1 c IS
CB2 c 19
v cc c 20
40 □ CA1
39 3 C A 2
38 3 IRQ
37 3 CNTR
38 3 RSO
35 □ RS1
34 3 R E S
33 3 DO
32 3 01
31 3 0 2
30 3 03
29 3 04
28 3 05
27 3 D6
26 □ 07
25 □ #2
24 □ RS2
23 □ CS2
22 U CSC
21 □ R/W
40-PIN DIP
A3 .3Q5. aS. o& z%><o 2o lis£ %o z9
n xm n n n n n n n n
/
PA4 C 7
PA5 L 8
PA8 C 9
o
PIN 1
INDICATOR
39
38
37
P A 7 c 10
PB O c 11
PB1 c 12
36
35
34
PB 2 c 13
PB3 L 14
33
32
PB4 c 15
31
PBS c 16
30
.. , „P B 6 c 17
« » O T- N
29
* W* N
PPMNNNNNNNN
U U ' U U U U LTLT U U LT
□ RSO
□ RS1
3 RES
3 DO
□ 01
□ 02
□ 03
□ 04
I! 05
□ 06
□ 07
£ 8 8 > 8* ? g l 8 S * -
44-PIN PCC
NC NO INTERNAL
CONNECTION
Figure 1. R65C24 Pin Assignments
Document No. 29651NS4
Product Description
1-75
Order No. 2151
Rev. 5, June 1987



R65C24
R65C24
Peripheral Interface Adapter/Timer (PIAT)
ORDERING INFORMATION
Part Number:
R6SC24
Temperature Range:
Blank = D°C to + 70°C
E = -4 0 °C to + 85°C
Frequency Range:
1 = 1 MHz
2 = 2 MHz
3 = 3 MHz
4 = 4 MHz
Package:
C = 40-Pin Ceramic DIP
P = 43-Pin Plastic DIP
j = 44-Pin Plastic Leaded
Chip Carrier (PLCC)
NOTE:
An R65C24 PIAT may be installed in a circuit in place of
an R65C21 PIA subject to chip select considerations. Since
the R65C21 has a CS1 input and the R54C24 does not
have a CS1 input, the PIAT will be selected in the same
addresses as the PIA and maybe more depending upon
external address decoding circuitry.
RESET SIGNAL (RES)
The Reset (RES) input initializes the R65C24 PIAT. A low signal
on the (RES) input causes all internal registers to be cleared.
CLOCK SIGNAL (02)
The Phase 2 Clock Signal (02) is the system clock that triggers
all data transfers between the CPU and the PIAT. 02 is generated
by the CPU and is therefore the synchronizing signal between
the CPU and the PIAT.
INTERFACE SIGNALS
The PIAT interfaces to the R6500, R6500/* or the R65COO
microprocessor family with a reset line, a 02 clock line, a
read/write line, an interrupt request line, three register select lirves,
two chip select lines, and an 8-bit bidirectional data bus.
The PIAT interfaces to the peripheral devices with four
interrupt/control lines and two 8-bit bidirectional data ports. A
Counter/Timer input/output line (CNTR) also interfaces to a
peripheral device.
Figure 1 (on the front page) shows the pin assignments for these
interface signals and Figure 2 shows the interface relationship of
these signal as they pertain to the CPU and the peripheral devices.
CHIP SELECT (CSO, CS2)
The PIAT is selected when CSO is high and CS2 is low. These
two chip select lines are normally connected to the processor
address lines either directly or through external decoder circuits.
When the PIAT is selected, data will be transferred between the
data lines and PIAT registers, and/or peripheral interface lines
as determined by the R/W, RSO, RS1 and RS2 lines and the
contents of Control Registers A and B.
READ/WRITE SIGNAL (R/W)
Read/Write (R/W) controls the direction of data transfers between
the PIAT and the data lines associated with the CPU and the
peripheral devices. A high on the R/W line permits the peripheral
devices to transfer data to the CPU from the PIAT. A low on the
R/W line allows data to be transferee) from the CPU to the
peripheral devices from the PIAT.
REGISTER SELECT (RSO, RS1, RS2)
Two of the Register Select lines (RSO, RS1), in conjunction with
the Control Registers (CRA, CRB), select various R65C24
registers to be accessed by the CPU. RSO and RS1 are normally
connected to the microprocessor (CPU) address output lines.
Through control o f these lines, the CPU can w rite directly into
the Control Registers (CRA, CRB), the Data Direction Registers
(DDRA, DDRB)and the Peripheral Output Registers (OFtA, ORB).
In addition, the processor may directly read the contents of the
Control Registers and the Data Direction Registers. Accessing
the Peripheral Output Register for ihe purpose of reading data
back into the processor operates differently on the ORA and the
ORB registers and, therefore, are shown separately in Table 1.
Figure 2. Interface Signals Relationship
1-76





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)