Communications Controller. R68561 Datasheet
R68560 • R68561
Controller (M PCe)
The R68560, R68561 Multi-Protocol Communications Controller
(MPCC) interfaces a single serial communications channel to
a 68008/68000 microcomputer-based system using either asyn-
chronous or synchronous protocol. High speed bit rate, auto-
matic formatting, low overhead programming, eight character
buffering, two channel DMA interface and three separate inter-
rupt vector numbers optimize MPCC performance to take full
advantage of the 68008/68000 processing capabilities and
asynchronous bus structure.
In synchronous operation, the MPCC supports bit-oriented
protocols (BOP), such as SDLC/HDLC, and character-oriented
protocols (COP), such as IBM Bisync (BSC) in either ASCII or
EBCDIC coding. Formatting, synchronizing, validation and error
detection is performed automatically in accordance with protocol
requirements and selected options. Asynchronous (ASYNC) and
isochronous (ISOC) modes are also supported. In addition,
modem interface handshake signals are available for general
Control, status and data are transferred between the MPCC and
the microcomputer bus via 22 directly addressable registers and
a DMA interface. Two first-in first-out (FIFO) registers, address-
able through separate receiver and transmitter data registers,
each buffer up to eight characters at a time to allow more MPU
processing time to service data received or to be transmitted
and to maximize bus throughput, especially during DMA oper-
ation. The two-channel Direct Memory Access (DMA) interface
operates with the MC68440/MC68450 DMA Controllers. Three
prioritized interrupt vector numbers separately support receiver,
transmitter and modem interface operation.
An on-chip oscillator drives the internal baud rate generator
(BRG) and an external clock output with an 8 MHz input crystal
or clock frequency. The BRG, in conjunction with two selecta-
ble prescalers and 16-bit programmable divisor, provides a data
bit rate of DC to 4 MHz.
The 48-pin R68561 supports word-length (16-bit) operation when
connected to the 68000 15-bit asynchronous bus, as well as byte-
length (8-bit) operation when connected to the 68008 8-bit bus.
The 40-pin R68560 supports byte-length operation on the 68008
• Full duplex synchronous/asynchronous receiver and transmitter
• Implements IBM Binary Synchronous Communications (BSC)
in two coding formats: ASCII and EBCDIC
• Supports other synchronous character-oriented protocols
(COP), such as six-bit BSC, X3.28k, ISO IS1745, ECMA-16, etc.
• Supports synchronous bit oriented protocols (BOP), such as
SDLC, HDLC, X.25, etc.
• Asynchronous and isochronous modes
• Modem handshake interface
• High speed serial data rate (DC to 4 MHz)
• Internal oscillator and baud rate generator with programma-
ble data rate
• Crystal or TTL level clock input and buffered clock output
• Direct interface to 68008/68000 asynchronous bus
• Eight-character receiver and transmitter buffer registers
• 22 directly addressable registers for flexible option selection,
complete status reporting, and data transfer
• Three separate programmable interrupt vector numbers for
receiver, transmitter and serial interface
• Maskable interrupt conditions for receiver, transmitter and
• Programmable microprocessor bus data transfer; polled, inter-
rupt and two.channel DMA transfer compatible with
• Clock control register for receiver clock divisor and receiver
and transmitter clock routing
• Selectable full/half duplex, autoecho and local loop-back
• Selectable parity (enable, odd, even) and CRC (control field
enable, CRC-16, CCITT V.41, VRC/LRC)
TLIPackage: C = Ceramic
P = Plastic
Number of pins: 0 = 40
1 = 48
O·C to 7O·C
Document No. 68650N06
Order No. 705
Rev. 6, June 1987
Multi-Protocol Communications Controller (MPCC)
TO Rx LOGIC
BAUD RATE GENERATOR
t - - - - - - - - - - - - - I - - - - - - TxC
1. R68560 ONLY.
2. R68561 ONLY.
3. UOS ON R68561 AD ON R68560
4. LOS ON R68561 OS ON R68560
Figure 1. MPCC Block Diagram
Throughout the document. signals are presented using the terms
active and inactive or asserted and negated independently of
whether the signal is active in the high·voltage state or low·
voltage state. (The active state of each logic pin is described
below.) Active low signals are denoted by a superscript bar. For
example. RiW indicates write is active low and read is active
Note: The R68561 interface is described for word mode opera·
tion only and the R68560 interface is described for byte
mode operation only.
A1-A4-Address Lines. A1-M are active high inputs used in
conjunction with the CS input to access the internal registers.
The address map for these registers is shown in Table 1.
DO-D15-Data Lines. The bidirectional data lines transfer data
between the MPCC and the MPU, memory or other peripheral
device. DO-D15 are used when connected to the 16·bit 68000
bus and operating in the MPCC word mode. DO-D7 are used
when connected to the 16·bit 68000 bus or the 8·bit 68008 bus
and operating in the MPCC byte mode. The data bus is three·
stated when CS is inactive. (See exceptions in DMA mode.)
Multi-Protocol Communications Controller (MPCC)
CS-Chip Select. CS low selects the MPCC for programmed
transfers with the host. The MPCC is deselected when the CS
input is inactive in non-DMA mode. CS must be decoded from
the address bus and gated with address strobe (AS).
RtW-ReadlWrite. Rm controls the direction of data flow
through the bidirectional data bus by indicating that the current
bus cycle is a read (high) or write (low) cycle.
DTACK-Oata Transfer Acknowledge. DTACK is an active
low output that signals the completion of the bus cycle. During
read or interrupt acknowledge cycles, DTACK is asserted by
the MPCC after data has been provided on the data bus; during
write cycles it is asserted after data has been accepted at the
data bus. DTACK is driven high after assertion prior to being
tri-stated. A holding resistor is required to maintain OTACK high
between bus cycles.
OS-Data Strobe (R6856D). During a write (R/Iii low), the
DS positive transition latches data on data bus lines DO-D7
into the MPCC. During a read (Rm high), DS low enables data
from the MPCC to data bus lines DO-D7.
LOS-Lower Data Strobe (R68561). During a write (Rm low),
the positive transition latches data on the data bus lines DO-D7
(and on D8-D15 if UDS is low) into the MPCC. During a read
(Rm high), LDS low enables data from the MPCC to DO-D7
(and to D8-D15 if UDS is lOW).
AD-Address Line AD (R68560). When interfaCing to an 8-bit
data bus system such as the 68008, address line AD is used
to access an internal register. AD = 0 defines an even register
and AD = 1 defines an odd register. See Table 1b.
UDS-Upper Data Strobe (R68561). When interfacing to a
16-bit data bus system such as the 68000, a low on control bus
signal UDS enables access to the upper data byte on D8-D15.
A high on UDS disables access to D8-Dt5. Data is latched and
enabled in conjunction with LDS.
IRQ-Interrupt Request. The active low IRQ output requests
interrupt service by the MPU. IRQ is driven high after assertion
prior to being tri-stated.
lACK-Interrupt Acknowledge. The active low lACK input
indicates that the current bus cycle is an interrupt acknowledge
cycle. When lACK is asserted the MPCC places an interrupt
vector on the lower byte (DO-D7) of the data bus.
TDSR-Transmitter Data Service Request. When Trans-
mitter DMA mode is active, the low TDSR output requests DMA
ROSR-Receiver Data Service Request. When receiver DMA
mode is active, the low RDSR output requests DMA service.
OACK-OMA Acknowledge. The DACK low input indicates
that the data bus has been acquired by the DMAC and that the
requested bus cycle is beginning.
OTC-Data Transfer Complete. On a 68000 bus, the DTC low
input indicates that a DMA data transfer was completed with no
bus conflicts. DTC in response to a RDSR indicates that the data
has been successfully stored in memory. DTC in response to
a TDSR indicates that the data is present on the data bus for
strobing into the MPCC. If not used, this input should be con-
nected to ground.
DSR } INTERFACE
Figure 2. MPCC Input and Output Signals