9ZX21901D Datasheet: 19-Output DB1900Z





9ZX21901D 19-Output DB1900Z Datasheet

Part Number 9ZX21901D
Description 19-Output DB1900Z
Manufacture IDT
Total Page 20 Pages
PDF Download Download 9ZX21901D Datasheet PDF

Features: 19-Output DB1900Z for PCIe Gen1-4 and QP I/UPI 9ZX21901D DATASHEET Description The 9ZX21901D is a second generation D B1900Z differential buffer for Intel Pu rley and newer platforms. The part is b ackwards compatible to the 9ZX21901C wh ile offering much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/U PI applications. In bypass mode, the 9Z X21901D can provide outputs up to 400MH z. PCIe Clocking Architectures Supporte d • Common Clocked (CC) • Separate Reference No Spread (SRNS) • Separate Reference Independent Spread (SRIS) Ty pical Applications • Servers, Storage , Networking Output Features • 19 HCS L output pairs Key Specifications • C ycle-to-cycle jitter: < 50ps • Output -to-output skew: < 50ps • Input-to-ou tput delay: Fixed at 0 ps • Input-to- output delay variation: < 50ps • Phas e jitter: PCIe Gen4 < 0.5ps rms • Pha se jitter: UPI 9.6GB/s < 0.1ps rms Fea tures • Fixed feedback path; 0ps input-to-output delay • 9 .

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19-Output DB1900Z for PCIe Gen1-4 and
QPI/UPI
9ZX21901D
DATASHEET
Description
The 9ZX21901D is a second generation DB1900Z differential
buffer for Intel Purley and newer platforms. The part is
backwards compatible to the 9ZX21901C while offering much
improved phase jitter performance. A fixed external feedback
maintains low drift for critical QPI/UPI applications. In bypass
mode, the 9ZX21901D can provide outputs up to 400MHz.
PCIe Clocking Architectures Supported
Common Clocked (CC)
Separate Reference No Spread (SRNS)
Separate Reference Independent Spread (SRIS)
Typical Applications
Servers, Storage, Networking
Output Features
19 HCSL output pairs
Key Specifications
Cycle-to-cycle jitter: < 50ps
Output-to-output skew: < 50ps
Input-to-output delay: Fixed at 0 ps
Input-to-output delay variation: < 50ps
Phase jitter: PCIe Gen4 < 0.5ps rms
Phase jitter: UPI 9.6GB/s < 0.1ps rms
Features
Fixed feedback path; 0ps input-to-output delay
9 Selectable SMBus addresses; multiple devices can share
same SMBus segment
8 dedicated OE# pins; hardware control of outputs
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL BW; minimizes jitter peaking in downstream
PLL's
Hardware or software control of PLL operating mode;
change mode with software mode does not need power
cycle
Spread spectrum compatible; tracks spreading input clock
for EMI reduction
SMBus Interface; unused outputs can be disabled
100MHz and 133.33MHz PLL mode; legacy QPI support
72-QFN 10 x 10 mm package; small board footprint
Functional Block Diagram
DIF_IN
OE(12:5)#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Low Phase
Noise Z-PLL
(SS-
Compatible)
Bypass path
IREF
DFB_OUT
DIF[18]
19 outputs
DIF[0]
9ZX21901D APRIL 17, 2018
1 ©2018 Integrated Device Technology, Inc.

                    
                    






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