9ZXL1530D Datasheet | 15-Output DB1900Z Derivative





9ZXL1530D PDF File (Datasheet) Download

Part Number 9ZXL1530D
Description 15-Output DB1900Z Derivative
Manufacture IDT
Total Page 23 Pages
PDF Download Download 9ZXL1530D PDF File

Features: 15-Output DB1900Z Derivative 9ZXL1530D / 9ZXL1550D for PCIe Gen1–4 and UPI Datasheet Description The 9ZXL1530D / 9ZXL1550D are second-generation enhance d-performance DB1900Z-derivative differ ential buffers. The parts are pin-compa tible upgrades to the 9ZXL1530B and 9ZX L1550B, while offering a much improved phase jitter performance. A fixed exter nal feedback maintains low drift for cr itical QPI/UPI applications. In fanout mode, the devices meet the DB2000Q addi tive phase jitter specification. PCIe Clocking Architectures ▪ Common Clock ed (CC) ▪ Independent Reference (IR) with and without spread spectrum Typic al Applications ▪ Servers ▪ Storage ▪ Networking ▪ SSDs Output Featur es ▪ 15 Low-Power HCSL (LP-HCSL) outp ut pairs (1530D) ▪ 15 Low-Power HCSL (LP-HCSL) output pairs with 85Ω Zout (1550D) Block Diagram VDDR VDDA Fea tures ▪ LP-HCSL outputs; eliminate 30 resistors, save 51mm2 of area (1530D) ▪ LP-HCSL outputs with 85Ω Zout; eliminate 60 resistors, sa.

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15-Output DB1900Z Derivative 9ZXL1530D / 9ZXL1550D
for PCIe Gen1–4 and UPI
Datasheet
Description
The 9ZXL1530D / 9ZXL1550D are second-generation
enhanced-performance DB1900Z-derivative differential buffers.
The parts are pin-compatible upgrades to the 9ZXL1530B and
9ZXL1550B, while offering a much improved phase jitter
performance. A fixed external feedback maintains low drift for
critical QPI/UPI applications. In fanout mode, the devices meet the
DB2000Q additive phase jitter specification.
PCIe Clocking Architectures
Common Clocked (CC)
Independent Reference (IR) with and without spread spectrum
Typical Applications
Servers
Storage
Networking
SSDs
Output Features
15 Low-Power HCSL (LP-HCSL) output pairs (1530D)
15 Low-Power HCSL (LP-HCSL) output pairs with 85Zout
(1550D)
Block Diagram
VDDR
VDDA
Features
LP-HCSL outputs; eliminate 30 resistors, save 51mm2 of area
(1530D)
LP-HCSL outputs with 85Zout; eliminate 60 resistors, save
103mm2 of area (1550D)
SMBus OE bits; software control of each output
9 selectable SMBus addresses; multiple devices can share the
same SMBus segment
Selectable PLL BW; minimizes jitter peaking in cascaded PLL
topologies
Hardware/SMBus control of PLL bandwidth and bypass;
change mode without power cycle
Spread spectrum compatible; tracks spreading input clock for
EMI reduction
9 × 9 mm 64-VFQFPN package; small board footprint
Key Specifications
Cycle-to-cycle jitter: < 50ps
Output-to-output skew: < 50ps
Input-to-output delay: fixed at 0ps
Input-to-output delay variation: < 50ps
Additive phase jitter: PCIe Gen4 < 53fs rms
Additive phase jitter: IF-UPI < 70fs rms
Additive phase jitter: DB2000Q filter < 30fs rms
VDD x3
VDDIO x4
DIF_IN#
DIF_IN
PLL
FBOUT_NC#
FBOUT_NC
DIF14#
DIF14
^100M_133M#
^SADR[1:0]_tri
SMBCLK
SMBDAT
SMBus
Factory
Engine Configuration
15
outputs
^vHIBW_BYPM-LOBW#
^CKPWRGD_PD#
Control Logic
GNDA
Resistors are integrated on 9ZXL1550 devices
and external on 9ZXL1530 devices.
GND x12
DIF0#
DIF0
©2019 Integrated Device Technology, Inc
1
February 14, 2019

                    
                    






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