9FGV1002B Datasheet: Low-Power Programmable PhiClock Generator





9FGV1002B Low-Power Programmable PhiClock Generator Datasheet

Part Number 9FGV1002B
Description Low-Power Programmable PhiClock Generator
Manufacture IDT
Total Page 16 Pages
PDF Download Download 9FGV1002B Datasheet PDF

Features: Low Phase-Noise, Low-Power Programmable PhiClock™ Generator 9FGV1002B Datash eet Description The 9FGV1002B is a mem ber of IDT's PhiClock™ programmable c lock generator family. The 9FGV1002B pr ovides four copies of a single integer, fractional or spread-spectrum frequenc y and two copies of the crystal referen ce input. Two select pins allow for har dware selection of the desired configur ation, or two I2C bits allow easy softw are selection of the desired configurat ion. The user may configure any one of the four OTP configurations as the defa ult when operating in I2C mode. Four un ique I2C addresses are available, allow ing easy I2C access to multiple compone nts. Typical Applications ▪ HPC ▪ S torage ▪ 10G/25G/100G Ethernet ▪ NV Link ▪ eSSDs Output Features ▪ 4 pr ogrammable output pairs plus 2 LVCMOS R EF outputs ▪ 1 integer, fractional or spread spectrum output frequency per c onfiguration ▪ 10MHz–325MHz LVDS or LP-HCSL outputs ▪ 10MHz–200MHz LVCMOS outputs Key Specific.

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Low Phase-Noise, Low-Power
Programmable PhiClock™ Generator
9FGV1002B
Datasheet
Description
The 9FGV1002B is a member of IDT's PhiClock™ programmable
clock generator family. The 9FGV1002B provides four copies of a
single integer, fractional or spread-spectrum frequency and two
copies of the crystal reference input. Two select pins allow for
hardware selection of the desired configuration, or two I2C bits
allow easy software selection of the desired configuration. The
user may configure any one of the four OTP configurations as the
default when operating in I2C mode. Four unique I2C addresses
are available, allowing easy I2C access to multiple components.
Typical Applications
HPC
Storage
10G/25G/100G Ethernet
NVLink
eSSDs
Output Features
4 programmable output pairs plus 2 LVCMOS REF outputs
1 integer, fractional or spread spectrum output frequency per
configuration
10MHz–325MHz LVDS or LP-HCSL outputs
10MHz–200MHz LVCMOS outputs
Key Specifications
274fs rms typical phase jitter at 156.25MHz (12kHz–20MHz)
< 0.2ps rms PCIe Gen4 Common Clocked jitter at 100MHz
Features
1.8V to 3.3V power supplies
Individual 1.8V to 3.3V VDDO for each output pair
Supports HCSL, LVDS and LVCMOS I/O standards
Supports LVPECL and CML logic with easy AC coupling – see
application note AN-891 for alternate terminations
HCSL utilizes IDT's LP-HCSL technology for improved
performance, lower power and higher integration:
Programmable output impedance of 85or 100
On-board OTP supports up to 4 complete configurations
Configuration selected via strapping pins or I2C
Internal crystal load capacitors
< 125mW at 1.8V with LP-HCSL outputs at 100MHz (LP-HCSL)
4 programmable I2C addresses: D0, D2, D4, D6
Supported by IDT Timing Commander™ software and Web
Configuration tool
Space saving 4 × 4 mm 24-VFQFPN package with integrated
crystal option (9FGV1002BQ)
Programmable spread spectrum modulation frequency and
amount
PCIe Clocking Architectures
PCIe Gen1–4 Common Clocked (CC)
Independent Reference without spread spectrum (SRnS)
Independent Reference with spread spectrum (SRnS)
Block Diagram
XIN/CLKIN
XO
Crystal is
integrated on
9FGV1002Q
VDDDp OTP_VPP
OSC
VDDAp
Fractional
PLL
(SSC)
INT
vSEL_I2C#
^SEL0/SCL
^SEL1/SDA
^OEB
^OEA
©2018 Integrated Device Technology, Inc.
SMBus
Factory
Engine Configuration
Control Logic
Internal terminations are available when LP -HCSL output format is selected .
EPAD/GND
1
REF1
REF0
VDDREFp
OUT3#
OUT3
VDDO3
OUT2#
OUT2
VDDO2
OUT1#
OUT1
VDDO1
OUT0#
OUT0
VDDO0
December 6, 2018

                    
                    






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