9FGL6251 Datasheet PDF | IDT





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Part Number 9FGL6251
Description Intelligent PCIe Clock Buffer/Generator
Manufacture IDT
Total Page 28 Pages
PDF Download Download 9FGL6251 Datasheet PDF

Features: Intelligent PCIe Clock Buffer/Generator for SSD 9FGL6241 / 9FGL6251 Datasheet Description The 9FGL6241 / 9FGL6251 ar e intelligent buffer/clock generators t ailored for single and dual-ported nVME SSDs. They support Common (CC) and Ind ependent Reference (IR) clocking archit ectures and are ideal for U.2 and M.2 f orm factors. The devices are also usefu l in PCIe master/slave and clock multip lexing applications, with an internal c lock generator as a third input channel . Typical Applications ▪ 1 × 4 and 2 × 2 nVME SSDs ▪ 3:2 PCIe clock mult iplexing Output Features ▪ Two 100MHz Low-Power HCSL (LP-HCSL) outputs with Zo = 100Ω or 85Ω ▪ One 33 1/3MHz or 25MHz 1.8V LVCMOS REF output ▪ One open drain CC_IR output indicates PCIe clock mode Features ▪ Supports sing le or dual-ported nVME drives ▪ Autom atically detects presence or absence of input clocks ▪ Integrated terminatio ns on LP-HCSL outputs save 8 resistors ▪ Choice of spread off (0% SRnS) or spread on (-0.5% SRIS) de.

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9FGL6251 datasheet
Intelligent PCIe Clock
Buffer/Generator for SSD
9FGL6241 / 9FGL6251
Datasheet
Description
The 9FGL6241 / 9FGL6251 are intelligent buffer/clock generators
tailored for single and dual-ported nVME SSDs. They support
Common (CC) and Independent Reference (IR) clocking
architectures and are ideal for U.2 and M.2 form factors. The
devices are also useful in PCIe master/slave and clock
multiplexing applications, with an internal clock generator as a
third input channel.
Typical Applications
1 × 4 and 2 × 2 nVME SSDs
3:2 PCIe clock multiplexing
Output Features
Two 100MHz Low-Power HCSL (LP-HCSL) outputs with Zo =
100or 85
One 33 1/3MHz or 25MHz 1.8V LVCMOS REF output
One open drain CC_IR output indicates PCIe clock mode
Features
Supports single or dual-ported nVME drives
Automatically detects presence or absence of input clocks
Integrated terminations on LP-HCSL outputs save 8 resistors
Choice of spread off (0% SRnS) or spread on (-0.5% SRIS)
default
Choice of 25MHz or 33 1/3MHz reference clock
REF clock output; saves external XO
2.5V to 3.3V operating voltage
1.8V compatible, 3.3V tolerant single-ended I/O signaling
Open-drain CC_IR output; maximum system flexibility
4 × 4 mm 28-VQFP-N package with external crystal
4 × 4 mm 28-LGA package with optional internal crystal
Key Specifications
DIF cycle-to-cycle jitter < 50ps
PCIe Gen1–4 (CC) compliant; Gen2–3 (IR) compliant
Block Diagram
VDDIN[A:B] VDDDIG VDDA VDDO1 VDDREF_1p8
XIN/CLKIN
XO
OSC
PLL
DIF_INA
DIF_INA#
REFOUT
DIF0#
DIF0
DIF_INB
DIF_INB#
DIF1#
DIF1
vePERst0#
vePERst1#
Input
Detect
Logic
CC_IR
SCLK_3.3
SDATA_3.3
SMBus Engine
Factory Configuration
Logic
POR
GNDIN[A:B] GNDDIG EPAD GNDREF GNDO[0:1]
©2018 Integrated Device Technology, Inc.
1
October 11, 2018

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