9FGV1008B Data Sheet PDF | IDT





(Datasheet) 9FGV1008B PDF Download

Part Number 9FGV1008B
Description Low-Power Programmable PhiClock Generator
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9FGV1008B Datasheet PDF

Features: Low Phase-Noise, Low-Power Programmable PhiClock™ Generator 9FGV1008B Datash eet Description The 9FGV1008B is a mem ber of IDT's PhiClock™ programmable c lock generator family. The 9FGV1008B pr ovides one integer frequency, one copy of a fractional or spread spectrum outp ut frequency, and one copy of the cryst al reference input. Two select pins all ow for hardware selection of the desire d configuration, or two I2C bits allow easy software selection of the desired configuration. The user may configure a ny one of the four OTP configurations a s the default when operating in I2C mod e. Four unique I2C addresses are availa ble, allowing easy I2C access to multip le components. Typical Applications ▪ HPC ▪ Storage ▪ 10G/25G/100G Ether net ▪ Fiber Optic Modules ▪ eSSDs K ey Specifications ▪ 224fs rms typical phase jitter at 156.25MHz (12kHz–20M Hz) ▪ PCIe Gen1–4 compliant (spread spectrum off) ▪ PCIe Gen1–3 compli ant (spread spectrum on) ▪ See AN-1001 for PCIe Gen4 applicat.

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9FGV1008B datasheet
Low Phase-Noise, Low-Power
Programmable PhiClock™ Generator
9FGV1008B
Datasheet
Description
The 9FGV1008B is a member of IDT's PhiClock™ programmable
clock generator family. The 9FGV1008B provides one integer
frequency, one copy of a fractional or spread spectrum output
frequency, and one copy of the crystal reference input. Two select
pins allow for hardware selection of the desired configuration, or
two I2C bits allow easy software selection of the desired
configuration. The user may configure any one of the four OTP
configurations as the default when operating in I2C mode. Four
unique I2C addresses are available, allowing easy I2C access to
multiple components.
Typical Applications
HPC
Storage
10G/25G/100G Ethernet
Fiber Optic Modules
eSSDs
Key Specifications
224fs rms typical phase jitter at 156.25MHz (12kHz–20MHz)
PCIe Gen1–4 compliant (spread spectrum off)
PCIe Gen1–3 compliant (spread spectrum on)
See AN-1001 for PCIe Gen4 applications requiring spread
spectrum
PCIe Clocking Architectures
Common Clocked (CC)
Independent Reference without spread spectrum (SRnS)
See AN-1001 for Independent Reference with spread-spectrum
(SRIS) applications
Features
1.8V–3.3V core VDD and VDDREF
Individual 1.8V–3.3V VDDO for each output pair
Supports HCSL, LVDS and LVCMOS I/O standards
Supports LVPECL and CML logic with easy AC coupling – see
AN-891 for alternate terminations
HCSL utilizes IDT's LP-HCSL technology for improved
performance, lower power and higher integration:
Programmable output impedance of 85or 100
On-board OTP supports up to 4 complete configurations
Configuration selected via strapping pins or I2C
Internal crystal load capacitors
< 135mW at 1.8V with outputs running at 100MHz (LP-HCSL)
4 programmable I2C addresses: D0, D2, D4, D6
Supported by IDT Timing Commander™ software and web
configurator
Space saving 3 × 3 mm 16-LGA package with integrated
crystal option (9FGV1008BQ)
Programmable spread spectrum modulation frequency and
amount
Output Features
2 programmable output pairs plus 1 LVCMOS REF output
1 integer output frequency and 1 fractional or spread spectrum
output frequency per configuration
10MHz–325MHz LVDS or LP-HCSL outputs
10MHz–200MHz LVCMOS outputs
10MHz–156.25MHz spread spectrum or fractional output
Block Diagram
XIN/CLKIN
XO
Crystal is
integrated on
9FGV1008BQ
vSEL_I2C#
^SEL0/SCL
^SEL1/SDA
©2018 Integrated Device Technology, Inc.
VDDDp OTP_VPP VDDAp VDDAO0p
OSC
INT
PLL
SMBus
Engine
Factory
Configuration
INT
DIV
FOD
(SSC)
REF0
VDDREFp
OUT1#
OUT1
VDDO1
OUT0#
OUT0
VDDO0
Control Logic
Internal terminations are available when LP-HCSL output format is selected.
EPAD/GND
1
October 1, 2018

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